Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-07-28
2001-04-24
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000, C438S398000, C257S607000
Reexamination Certificate
active
06221705
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of passivating silicon bonds in semiconductor devices by a species, particularly deuterium.
2. Brief Description of the Prior Art
It is known that channel hot carrier (CHC) effects progressively degrade the performance of transistors, this effect being particularly apparent in VLSI CMOS transistors. Specifically, for any given bias condition, the channel current decreases over time. This aging process is thought to occur, in part, as a result of hot electrons stimulating the desorption of hydrogen from the Si/SiO
2
interface region. Hydrogen is introduced by necessity during several device processing steps, for example during the sintering of wafers at an elevated temperature in a hydrogen ambient.
To avoid the problems resulting from hot carrier effects, the drain voltage and gate length of the transistors must not be changed beyond certain values. This limits the performance of the transistor. By reducing the degradation from hot carrier effects, the design limits of the transistor are improved and a higher performance, more reliable transistor is achieved. While this process improves device function, it sets the stage for subsequent hot electron degradation.
In an article entitled “Reduction of hot electron degradation in metal oxide semiconductor transistors by deuterium processing” by J. W. Lyding et al.,
Applied Physics Letters,
Vol. 68, No. 18, Apr. 29, 1996, it is noted that replacing hydrogen with deuterium during the final wafer sintering process reduces hot electron degradation effects in metal oxide semiconductor transistors. The exact cause of this large isotope effect was not known. This substitution increased the CHC lifetime of the transistor by factors of 10 to 50, this being borne out by the applicants herein. However, Lyding et al. delivered the deuterium to the region of the gate oxide in an oven through thermal diffusion. This causes most of the deuterium to be wasted. In addition, during the sintering process, the deuterium may experience difficulty diffusing through some materials to reach the Si/SiO
2
interface, especially in those cases where several layers of metalization are located between the deuterium implant and the Si/SiO
2
interface.
It is also known in the case of flash memories which include a pair of insulator layers (interpolysilicon oxide layer and tunnel oxide layer) interleaved with a pair of polysilicon layers or the like, that each time the flash memory is written into or erased, charge moves through the dielectric layers surrounding the hanging polysilicon layer. This charge movement, over time, leads to a degradation of the electrical properties of the dielectric. This degradation can lead to charge loss on the storage cell, which can cause data loss. It is highly desirable to improve the quality of these surrounding dielectric layers to prevent or at least minimize this problem.
There has been no known solution to completely eliminate the wearout of the dielectric in flash memories. Generally, attention has been focused on improving the quality of the oxide or on optimizing the operation.
SUMMARY OF THE INVENTION
It is therefore a purpose of this invention to improve by ion or neutral implantation of deuterium the hot carrier lifetimes of MOS transistors with gates containing a silicon trioxide gate oxide as well as to improve the data retention characteristics of flash memory cells.
Although the gate insulator material herein is referred to as SiO
2
, it is to be understood that the invention also applies to gates that also contain nitrides or are solely comprised of nitrides or that include other possible gate insulator materials, such as, for example, tantalum pentoxide.
Briefly, in accordance with the present invention, deuterium is introduced into the semiconductor device by implantation, instead of by thermal diffusion as was done by Lyding et al. The implantation may be accomplished at any step of the semiconductor process flow. Examples with be provided hereinbelow. In general, deuterium implantation is provided so that, during subsequent thermal cycles, the deuterium will diffuse to the gate oxide/silicon interface and become chemically attached to the dangling bonds at that interface, this generally being the Si/SiO
2
or polysilicon/SiO
2
interface. The energy, dose and point defects of the implant are optimized to effect this.
The following are examples in which implantation is used to introduce deuterium to the structure, although many other possibilities will be readily apparent. These and other imnplants may be used in combination. (1) When the last metal level is completed, deuterium can be implanted into the inter-level dielectric, typically but not limited to an oxide, and then annealed in standard manner. (2) When the side-wall material is deposited, deuterium may be implanted into the side-wall material to add-to and/or displace the existing hydrogen in the side-wall material. (3) Deuterium may be implanted at any point in the process flow into the polysilicon that comprises the transistor gate which is above the gate oxide. (4) Deuterium may be implanted into the silicon, below the gate oxide, in the region that comprises the channel of the transistor at any point in the process flow.
By the method in accordance with the present invention, less deuterium gas is consumed as compared with the above described prior art. Ion implantation reduces isotopic contamination from hydrogen and tritium and, thereby, reduces CHC degradation from hydrogen and reliability problems from tritium decay, such as soft error rates (SER).
With reference to the flash memories, it is believed that the dielectric wearout is due to the accumulation of unpassivated defect sites in the oxide and that deuterium is less likely to be removed from these cites than is hydrogen. Anneals in a deuterium-containing, essentially hydrogen-free ambient, such as from about 10 percent to about 100 percent by volume deuterium and the remainder a gas inert to the operations being conducted, preferably nitrogen passivate defect sites with the deuterium. The deuterium is less likely to dissociate from the defect site and move through the structure than is hydrogen due to the difference in mass therebetween. Annealing will take place at a temperature above the dissociation temperature for hydrogen and silicon, this being above about 500 degrees C. for a period of from about 15 to about 30 minutes and preferably about 15 minutes.
REFERENCES:
patent: 5872387 (1999-02-01), Lyding et al.
patent: 5877051 (1999-03-01), Manning
patent: 5960294 (1999-09-01), Zahurak et al.
Harvey Kenneth C.
Rost Timothy A.
Brady III Wade James
Elms Richard
Luu Pho
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Method for improving performance and reliability of MOS... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for improving performance and reliability of MOS..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for improving performance and reliability of MOS... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2532468