Method for improving latch-up immunity and interwell isolation i

Details Method for improving latch-up immunity and interwell isolation i Method for improving latch-up immunity and interwell isolation i

1996-08-15

2000-01-25

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438217, 438223, 438224, 438225, 438226, 438227, 438228, 438531, 438981, H01L 218238

Patent

active

060177853

ABSTRACT:
A method of improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, an implant mask which has a variable permeability to implanted impurities is formed on the surface of a substrate having a first dopant region. A first portion of the implant mask overlies a first portion of the first dopant region. The structure is subjected to high energy implantation which forms a heavily doped region. A first portion of the heavily doped region is located along the lower boundary of the first dopant region. A second portion of the heavily doped region which extends along a side boundary of the first dopant region is formed by impurity ions which pass through the first portion of the implant mask. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance. In alternative embodiments, one variable permeability mask is used to form the first dopant region and also to form the heavily doped region continuous with the first dopant region.

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Toshiki Yabu et al., "An Advanced Half-Micrometer CMOS Device with Self-Aligned Retrograde Twin-Wells and Buried p.sup.+ Layer," VLSI Technology Symposium, pp. 35-36 (1989).
Photocopy of materials presented at a seminar hosted by Genus, Inc. on Jul. 12, 1995 in San Francisco, California entitled, "Manufacturing Issues (Process & Equipment) in MeV Implantation", John O. Borland.
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