Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-20
2001-05-22
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S306000, C438S307000, C438S515000
Reexamination Certificate
active
06235600
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to an ion implantation procedure, used to improve the reliability of metal oxide semiconductor field effect transistor, (MOSFET), devices, in regards to a hot electron carrier phenomena.
(2) Description of Prior Art
Micro-miniaturization has allowed the semiconductor industry to fabricate MOSFET devices with sub-quarter micron features. Specific MOSFET devices, such as input/output, N channel, (I/O NMOS), devices, used for logic applications, can however be prone to a hot electron carrier, (HCE), reliabiltty phenomena. The I/O NMOS devices, operating at a voltage of 3.3, or 2.5 volts, can suffer gate insulator degradation, as a result of hot electron injection at these operating voltages. The substrate current, or drain current specifications are therefore difficult to satisfy, as a result of the HCE phenomena, for sub-quarter micron, I/O NMOS devices, operating at 3.3, or 2.5 volts. Methods of anmealing the gate insulator layer, in an NO or N
2
O ambient, have not resulted in reductions in substrate current, (Isub), while other methods such as only providing a more graded, lightly doped source/drain, (LDD), region, have also not delivered the improved reliability of I/O NMOS devices, regarding HCE injection.
This invention will describe a novel process used to alleviate HCE injection, entailing the implantation of nitrogen, (N
2
), or nitrogen ions, (N
+
), either prior to, or after deposition of a silicon oxide layer, obtained using tetraethylorthosilicate, (TEOS), as a source, with the TEOS layer used as a liner layer, prior to formation of composite insulator spacers. The nitrogen implantation, located adjacent to the gate structure, and at the interface of a silicon oxide layer, underlying the composite insulator spacer, and an underlying lightly doped source/drain region, reduces HCE injection, as a result of nitrogen pile-up, at this interface. In addition the unplantation procedure allows an increase in transient enhanced diffusion, (TED), to occur, resulting in a greater degree of LDD grading, than offered by counterparts fabricated without this nitrogen implant, thus reducing Isub, indicating a reduction of HCE injection. Prior art, such as Gardner et al, in U.S. Pat. No. 5,994,175, as well as Arai et al, in U.S. Pat. No. 5,972,783, describe nitrogen implantation prior to LDD formation, not however describing this present invention of implanting nitrogen, post LDD implantation, performed either prior to, or after deposition of a TEOS liner, used underlying a subsequent composite insulator layer.
SUMMARY OF THE INVENTION
It is an object of this invention to improve the reliability of sub-quarter micron, I/O NMOS devices, operating at 3.3 and at 2.5 volts, via reducing HCE injection.
It is another object of this invention to implant nitrogen, or nitrogen ions, near the top surface of the LDD region, prior to, or after, deposition of a TEOS oxide layer, to be used a TEOS liner, underlying a subsequently formed composite insulator sidewall spacer.
It is still another object of this invention to ion implant the LDD dopants, than in situ implant nitrogen, prior to, or after, deposition of the TEOS liner.
In accordance with the present invention, a method of implanting nitrogen, near the top surface of an LDD region, prior to, or after deposition of a TEOS liner, is described. A first iteration of this invention entails forming a polysilicon gate structure, on an underlying silicon dioxide gate insulator layer, and after an polysilicon re-oxidation step, a photoresist shape is used to block MOSFET core devices from an implantation procedure used to create an LDD region for I/O NMOS devices. After deposition of a silicon oxide layer, using TEOS as a source, another photoresist shape is again used to block core MOSFET devices, from a N
2
or a N
+
implantation procedure, placing the implanted species at a silicon oxide layer—LDD interface, for the I/O NMOS devices. Deposition of a silicon oxide layer, and of a silicon nitride layer, are followed by an anisotropic reactive ion etching, (RIE), procedure, resulting in a composite insulator spacer, overlying the TEOS liner, and on the sides of the I/O NMOS polysilicon gate structure, and overlying the nitrogen implanted, LDD region.
A second iteration of this invention uses only one photoresist shape, to block the MOSFET core devices, from a series of in situ ion implantation procedures, comprising the implant procedure used to form the I/O NMOS, LDD region, followed by the in situ nitrogen implant. These implantations can be performed prior to, or after deposition of the TEOS liner.
REFERENCES:
patent: 5885877 (1999-03-01), Gardner et al.
patent: 5920782 (1999-07-01), Shih et al.
patent: 5972783 (1999-10-01), Arai et al.
patent: 5994175 (1999-11-01), Gardner et al.
Chiang Mu-Chi
Lin Hsien-Chin
Shih Jiaw-Ren
Ackerman Stephen B.
Pham Long
Saile George O.
Taiwan Semiconductor Manufacturing Company
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