Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-25
2001-05-29
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S529000
Reexamination Certificate
active
06238975
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of improving electrostatic discharge (ESD) robustness in a semiconductor integrated circuit, and more particularly, to a method of improving ESD robustness in a non-volatile memory
BACKGROUND ART
Conventional non-volatile memory devices have long had problems in overcoming their susceptibility to damage by electrostatic discharge (ESD). Conventional ESD protection structures have been developed for non-volatile memory devices with some degree of ESD protection. For example, lightly doped drain (LDD) implant techniques have been developed to offer some degree of protection against ESD. However, the conventional LDD implant techniques are capable of offering only limited ESD protection and would not be able to meet stringent ESD robustness requirements. For example, it would be difficult for a conventional n-channel metal oxide semiconductor (NMOS) transistor with a lightly doped drain to meet voltage specifications of 2 kV in a human body model (HBM) and 1 kV in a charge device model (CDM).
Conventional medium doped drain (MDD) implant techniques have been developed to increase the ESD robustness of conventional MOS peripheral devices. However, conventional NMOS transistor devices produced by the conventional MDD implant techniques may have high input leakage currents with low breakdown voltages due to shortened channels caused by greatly increased lateral diffusion resulting from the conventional MDD implantation. Since the lateral diffusion may be very fast in a conventional MDD implant process, it may be difficult to control the effective channel length of the conventional NMOS transistors with MDD implant.
Other conventional techniques have been developed to control program and erase characteristics of non-volatile memory devices by applying additional process steps of implantation to change the doping profiles of the sources and the drains of the core memory cells. However, adding process steps to improve ESD robustness of peripheral MOS devices may adversely affect the performance and reliability of the core memory cells.
Therefore, there is a need for a method of improving the ESD robustness of a non-volatile memory device which offers a high degree of reliable ESD protection without an excessive leakage current. Furthermore, there is a need for a simplified process for improving the ESD robustness of a non-volatile memory device without affecting the doping profiles in the core memory cells
DISCLOSURE OF THE INVENTION
The present invention satisfies these needs In a non-volatile memory comprising a region for core memory cells and a peripheral region on a substrate, the peripheral region including source and drain regions of at least one transistor the source and drain regions of said at least one transistor separated by a channel region, a method according to the present invention for improving electrostatic discharge (ESD) robustness of the non-volatile memory generally comprises the steps of:
(a) lightly doping the source and drain regions with a first dopant;
(b) providing a double-diffusion implant mask having an opening over the region for the core memory cells and an opening over the peripheral region; and
(c) performing a double-diffusion implantation through the opening over the peripheral region, the step of performing the double-diffusion implantation comprising the steps of:
(i) implanting a second dopant into the source and drain regions; and
(ii) implanting a third dopant into the source and drain regions subsequent to the step of implanting the second dopant.
In an embodiment in which the transistor in the peripheral region comprises an n-channel metal oxide semiconductor (NMOS) transistors the first, second and third dopants comprise firsts second and third n-type dopants, respectively In a further embodiment, the second and third n-type dopants used in the step of performing the double diffusion implantation comprise phosphorus and arsenic, respectively. In yet a further embodiment, the second n-type dopant is implanted into the source and drain regions of the peripheral transistor with an implant dose in the range of about 3×10
15
cm
−2
to about 6×10
15
cm
−2
, and the third n-type dopant is implanted into the source and drain regions with an implant dose in the range of about 1×10
14
cm
−2
to about 3×10
14
cm
−2
.
In a further embodiment, the first dopant comprises phosphorus which is implanted into the source and drain regions with an implant dose on the order of about 3×10
15
cm
−2
. In a further embodiment, the first n-type dopant is diffused into the source and drain regions to a depth on the order of about 0.2 &mgr;m. The double infusion implantation pushes the second and third n-type dopants slightly further into the source and drain regions of the substrates for example, to a depth on the order of about 0.23 &mgr;m.
In an embodiments the method according to the present invention further comprises the step of providing a gate oxide on the channel region of the substrate. In a further embodiment, the method further comprises the step of providing a gate on the gate oxide prior to the step of lightly doping the source and drains with the first dopant. In yet a further embodiment, the method further comprises the step of providing a spacer oxide surrounding the gate. The gate may be a polysilicon gate having a length on the order of about 1.1 &mgr;m, and the channel region may have an effective channel length of about 0.7 &mgr;m after the double diffusion implantation process is completed.
Advantageously, the present invention provides a method of improving the ESD robustness of a non-volatile memory to allow it to withstand a high-voltage electrostatic discharge. A further advantage of the present invention is that it is able to offer a high level of ESD protection without producing a high leakage current at a low breakdown voltage. Yet a further advantage of the present invention is that both the peripheral transistors and the core memory cells are subjected to the additional steps of double diffusion dopant implantation, thereby obviating the need for changing the doping profile of the sources and drains of the core memory cells solely for the purpose of ESD protection.
A further advantage of the present invention is that it uses an existing process and masking operations which was previously done specifically for the core memory cells, to improve also the ESD robustness of the peripheral transistors thereby obviating the need for additional processing and masking operations, which would otherwise add manufacturing cost and potentially decrease reliability of the core memory cells.
REFERENCES:
patent: 5622886 (1997-04-01), Allum et al.
patent: 5780893 (1998-07-01), Sugaya
patent: 5930628 (1999-07-01), Chang
patent: 6004843 (1999-12-01), Huang
patent: 43 33 768 (1994-04-01), None
patent: 0 273 728 (1988-07-01), None
Fliesler Michael David
Randolph Mark W.
Advanced Micro Devices , Inc.
Booth Richard
Fliesler Dubb Meyer & Lovejoy LLP
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