Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-14
2002-08-20
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S256000, C438S254000, C438S396000
Reexamination Certificate
active
06436762
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a process for making capacitor-under-bit-line devices having increased memory cell density, and more specifically the process employs a selective wet etch-back of portions of the top capacitor electrode (also referred to as cell plate) between adjacent capacitors. This etch-back increases the overlay margins of the bit-line contacts to the capacitors to reduce electrical shorts and allows the capacitors to be spaced closer to each other for increased memory cell density.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) circuits are used extensively in the electronics industry for storing date. The DRAM circuit includes an array of memory cells, each cell consisting of a single capacitor and a single transfer transistor. Typically the transfer transistor is a field effect transistor (FET). Binary data (1's and 0's ) are stored as charge on the capacitors, and the transfer transistor is used to retain the charge. During the read cycle the transfer transistor is used to interrogate the cell by means of bit lines. Two types of memory cells that are commonly used include a cell having a trench capacitor formed in the substrate under the PETs, and a cell having a stacked capacitor that is built over and between FETs. In the fabrication of DRAM circuits having stacked capacitors, the capacitor can be formed over the bit lines, commonly referred to as Capacitors-Over-Bit-lines (COB), or under the bit lines,.commonly referred to as Capacitors-Under-Bit lines (CUB). For all of the DRAM structures described above, the number of memory cells on a DRAM chip has increased dramatically over the years, and after the year 2000 the number of cells is expected to exceed 1 Gigabit. This increase is a result of the downsizing of the discrete devices using improved high-resolution photolithography, improved directional plasma etching, and self-aligning techniques, with a resulting increase in circuit density.
Numerous approaches to making these high-density circuits have been reported in the literature. For example, in U.S. Pat. No. 6,077,738 to Lee et al. a method is described for making DRAM devices (chips) which provides a global planar surface over the peripheral areas of the chip by using a thin silicon nitride layer. In U.S. Pat. No. 6,004,857 to Hsiao et al. a method is described for making a DRAM capacitor with a rough surface on the storage node plate (capacitor bottom electrode) for increased capacitance. In U.S. Pat. No. 6,127,260 to Hung a method is described for making tee-shaped contact openings to reduce the high aspect ratio on embedded DRAM devices. And in U. S. Pat. No. 5,893,734 to Jeng et al. a method is described for making multilevel contacts using a tungsten landing plug contact on CUB DRAM devices. However, none of the above cited references addresses the need to increase cell density by improving the overlay margins.
Although downscaling of devices and self-aligning techniques have dramatically increased the memory cell density on DRAM chips, there is still a strong need in the industry to further improve the reliability and further increase the cell density by other means. For example, it is highly desirable to further increase reliability by improving the overlay margins at various processing steps during the manufacture of DRAM circuits, and more particularly by increasing the overlay margin between the capacitors and the bit-line contacts.
SUMMARY OF THE INVENTION
A principal object of the present invention is to form an array of closely spaced dynamic random access memory (DRAM) cells, with reduced capacitor-to-bit-line shorts and increased cell density, for Capacitor-Under-Bit line (CUB) DRAM circuits.
Another object of this invention is to form these closely spaced memory cells by improving the overlay margin between the bit-line contact and the capacitor top electrode (capacitor cell plate).
Still another objective of this invention is to utilize a selective wet etch-back of portions of the polysilicon capacitor top electrode between adjacent capacitors to provide additional space for reducing the required overlay margin between the bit-line contact and the capacitor top electrode.
In accordance with the present invention, a method is described for making an array of crown-shaped capacitors under bit lines that have an improved overlay margin between the bit-line contacts and the capacitor top electrodes. The method for making the array of memory cells begins by providing a semiconductor substrate having partially completed DRAM devices. Typically the substrate is a single-crystal-silicon substrate doped with a P type conductive dopant, such as boron (B). Shallow trench isolation (STI) regions are formed surrounding and electrically isolating an array of device areas for memory cells on the substrate. The STI is formed by etching shallow trenches in the substrate, and the trenches are filled with an insulating material, such as silicon oxide (SiO
x
) and is polished back to a planar surface. The partially completed DRAMs also include field effect transistors (FETs) in the device areas. Typically the FETs consist of a thin gate oxide on the device areas, and gate electrodes formed from a patterned polycide layer. The FETs also have source/drain areas, one on each side and adjacent to the FET gate electrodes.
Continuing, a relatively thin conformal silicon nitride (Si
3
N
4
) barrier layer is formed over the device areas and over the STI regions to insulate the FET devices on the DRAM circuit. An interpolysilicon oxide (IPO) layer is deposited on the substrate, and conducting first and second plug contacts are formed concurrently in the IPO layer to contact the source/drain areas of the FETs. The conducting first plug contacts extend through the IPO layer to the first source/drain areas for capacitors, and the conducting second plug contacts extend through the IPO layer to the second source/drain areas for bit-line contacts. A capacitor-node oxide layer is deposited, and first openings are formed in the capacitor-node oxide layer aligned over the first conducting plug contacts. Capacitor bottom electrodes are formed in the first openings aligned over and contacting the first conducting plug contacts. For example, the bottom electrodes are formed by depositing a conformal conductively doped polysilicon layer over the first openings and polishing back. The capacitor-node oxide layer is then partially etched back to expose the top portions of the capacitor bottom electrodes. Additionally, a hemispherical silicon grain (HSG) layer can be formed on the bottom electrodes to increase the surface area for increased capacitance. A conformal interelectrode dielectric layer is formed on the substrate and over the bottom electrodes. A conformal conducting layer, such as a doped polysilicon, is then deposited to form capacitor top electrodes. Next a patterned photoresist mask and anisotropic etching are used to etch openings in the conformal conducting layer, aligned over the second conducting plug contacts. A key feature of the invention is now to use an isotropic etch to recess (selectively etch) the conformal conducting layer (capacitor top electrodes) under the photoresist mask to increase the critical dimensions for the second openings (bit-line openings), and then the patterned photoresist mask is removed. An interlevel dielectric (ILD) layer is deposited on the substrate. Bit-line contact openings are etched in the ILD layer aligned over and within the recessed (enlarged) openings in the conducting layer. The etching is continued through the capacitor-node oxide layer to the second plug contacts. The enlarged recessed openings in the conformal conducting layer result in increased alignment tolerances for improved electrical isolation margin between the capacitor top electrodes and the bit-line contacts. This provides greater design latitude in the ground rules and also allows for increased memory cell density. Bit-line conducting plugs are formed in the bit
Chang Chung-Wei
Chiang Min-Hsiung
Tseng Hsiao-Hui
Tzeng Kuo-Chyuan
Ying Tse-Liang
Ackerman Stephen B.
Lebentritt Michael S.
Saile George O.
Taiwan Semiconductor Manufactoring Company
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