Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Patent
2000-02-11
2000-11-07
Hardy, David
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
H01L 23544
Patent
active
061441090
ABSTRACT:
A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a planar-surfaced layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the planar-surfaced layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers. The aforementioned method and resulting structures can be further modified by forming an additional layer of material, having the requisite intermediate index of refraction, over an uppermost layer to further reduce reflection occurring at the interface between the uppermost layer and air. The invention is also directed to semiconductor devices, assemblies or laminates formed through the aforementioned methods and incorporating the aforementioned structures.
REFERENCES:
patent: 4389534 (1983-06-01), Winterling
patent: 5160957 (1992-11-01), Ina et al.
patent: 5528372 (1996-06-01), Kawashima
patent: 5532871 (1996-07-01), Hashimoto et al.
patent: 5541037 (1996-07-01), Hatakeyama et al.
patent: 5578519 (1996-11-01), Cho
patent: 5639687 (1997-06-01), Roman et al.
patent: 5700732 (1997-12-01), Jost et al.
patent: 5719072 (1998-02-01), Sugiura et al.
patent: 5731234 (1998-03-01), Chen
patent: 5760483 (1998-06-01), Bruce et al.
patent: 5847468 (1998-12-01), Nomura et al.
patent: 5895259 (1999-04-01), Carter et al.
patent: 5925937 (1999-07-01), Jost et al.
patent: 5933743 (1999-08-01), New et al.
patent: 5969428 (1999-10-01), Nomura et al.
patent: 6046094 (2000-04-01), Jost et al.
patent: 6060785 (2000-05-01), New et al.
Parekh Kunal R.
Stanton William A.
Wald Phillip G.
Cruz Lourdes
Hardy David
Micro)n Technology, Inc.
LandOfFree
Method for improving a stepper signal in a planarized surface ov does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for improving a stepper signal in a planarized surface ov, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for improving a stepper signal in a planarized surface ov will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1644224