Method for improved MOS gating to reduce miller capacitance...

Details Method for improved MOS gating to reduce miller capacitance... Method for improved MOS gating to reduce miller capacitance...

2006-02-28

2006-02-28

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S589000

Reexamination Certificate

active

07005353

ABSTRACT:
A method for reducing miller capacitance and switching losses in an integrated circuit includes providing a switching gate electrode having respective portions that are coplanar with the source and well regions of the integrated circuit. The switching gate electrode is configured for switching the integrated circuit on and off in response to a relatively small change in applied voltage. A shielding gate electrode is formed with respective portions coplanar with the switching electrode and the well region. The shielding electrode is configured for charging the gate-to-drain overlap region of the integrated circuit.

REFERENCES:
patent: 4735914 (1988-04-01), Hendrickson et al.
patent: 4941026 (1990-07-01), Temple
patent: 6285060 (2001-09-01), Korec et al.

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