Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-07-12
2004-08-31
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S674000
Reexamination Certificate
active
06784104
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to the field of semiconductor devices and fabrication and more specifically to a method for forming improved copper structures.
BACKGROUND OF THE INVENTION
To increase the operating speed, high performance integrated circuits use copper interconnect technology. Currently the damascene method is the most widely used method for forming copper interconnects. Using this methodology trenches
40
are first formed in a dielectric layer
20
as shown in FIG.
1
(
a
). As illustrated in FIG.
1
(
a
) the dielectric layer
20
is formed over a top layer
10
which is formed over a semiconductor substrate containing numerous electronic devices such as transistors, diodes, resistors, etc. In some cases the top layer
10
is a dielectric layer. The trench
40
is typically formed using a plasma based etching process and is defined using a patterned photoresist layer
30
.
Following the removal of the photoresist layer
30
a liner film
50
is formed in the trench as shown in FIG.
1
(
b
). Following the formation of the liner film
50
, copper is used to fill the trench resulting in the copper interconnect structure
60
shown in FIG.
1
(
b
). The process used to form the copper interconnect structure
60
comprises forming a thick copper layer using a bulk copper fill process followed by chemical mechanical polishing (CMP) to remove the excess copper.
Copper electroplating has become the most widely used approach for the bulk copper fill process. However, electroplated copper is unstable after plating and will undergo grain growth transformation even at room temperature. This grain growth process is beneficial in many ways to the properties of the copper interconnects. Some of these beneficial properties include lower resistivity and better electromigration reliability. The grain growth process is very geometry dependent with smaller film geometries underoging a much slower transformation process compared to larger film geometries. A comparison of the transformation of blanket copper films is shown in
FIG. 2
as a function of film thickness. The measured resistivity of the copper films is representative of the grain growth taking place in the film. As shown in
FIG. 2
, grain growth in thinner films takes place at a much slower rate than thicker films, indicating a slower rate of grain growth (regrowth). Shown in
FIG. 3
is the percentage reduction in resistance for a 0.75 &mgr;m blanket film
80
and a copper line
90
which is 0.35 &mgr;m wide and 0.8 &mgr;m thick. The copper line
90
has a much slower rate of grain growth (regrowth or transformation) compared to the blanket film
80
.
As integrated circuit technology advances, the width of the copper interconnect structures (
70
in FIG.
1
(
b
)) and the thickness of these structures (
75
in FIG.
1
(
b
)) will decrease. As this happens the electroplated copper used to form the copper interconnects will be harder to transform. It has been found that if the copper used to form these interconnect structures is not fully transformed, high resistivity and low electromigration resistance will lead to low device yield. There is therefore a need for a method which would result in fully transformed copper in damascene structures for thickness down to 0.1 &mgr;m and below.
SUMMARY OF THE INVENTION
The present invention describes an improved method for electroplating copper in integrated circuit technology. The method comprises providing a dielectric layer formed over a semiconductor wafer containing electronic devices such as transistors, capacitors etc. Copper lines are formed in the dielectric layer by first forming a trench in the dielectric layer. A barrier layer of titanium nitride or other suitable material is then formed in the trench. Before the electroplating process is performed a copper seed layer is formed on the barrier layer. With the surface of the copper seed layer acting as the cathode, the copper seed layer is placed in a electrolytic solution containing copper. An electrode is also placed in the electrolytic solution opposite the copper seed layer and a negative potential is applied to the copper seed layer while a positive potention is applied to the electrode. During the electroplating process the electrolytic solution is maintained at a temperature below about 25° C. This results is copper layers with reduced resistivity and improved stability.
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patent: 5933758 (1999-08-01), Jain
patent: 6024856 (2000-02-01), Haydu et al.
patent: 6030693 (2000-02-01), Boyko et al.
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patent: 6103624 (2000-08-01), Nogami et al.
patent: 0 952 242 (1999-10-01), None
patent: 1 152 071 (2001-11-01), None
Jiang Qing-Tang
Lu Jiong-Ping
Brady III W. James
McLarty Peter K.
Nguyen Ha Tran
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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