Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-04-26
2009-06-30
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000
Reexamination Certificate
active
07555688
ABSTRACT:
A method for implementing test generation for systematic scan reconfiguration in an integrated circuit is presented. The method may comprise: defining at least one set of detectable faults; setting an SAS decoder configuration, the SAS decoder configuration including a don't-care bit; generating an ATPG pattern; and applying the ATPG pattern to one or more scan chain segments having a segment address associated with the SAS decoder configuration.
REFERENCES:
patent: 5414716 (1995-05-01), Bershteyn
patent: 6041429 (2000-03-01), Koenemann
patent: 7093175 (2006-08-01), Rajski et al.
patent: 7143324 (2006-11-01), Bratt et al.
patent: 7178078 (2007-02-01), Hiraide et al.
patent: 7237162 (2007-06-01), Wohl et al.
patent: 2004/0153978 (2004-08-01), Xiang et al.
patent: 2005/0240887 (2005-10-01), Rajski et al.
patent: 2006/0020862 (2006-01-01), Kang et al.
“LFSR-Coded Test patterns for Scan Designs,” by Dr. Bernd Konemann; c/o IBM Corp., B56/901, P.O. Box 390, Poughkeepsie, NY 12533; European Test Conference (ETC'91); pp. 237-242; 1991.
“Seed Encoding with LFSRs and Cellular Automata,” by Ahmad A. Al-Yamani and Edward J. McCluskey; Center for Reliable Computing, Stanford University, Stanford, CA; 40th Design Automation Conference (DAC 2003); pp. 560-565; Jun. 2-6, 2003, Anaheim, CA; © 2003.
“CircularScan: A Scan Architecture for Test Cost Reduction,” by Baris Arslan and Alex Orailoglu; Computer Science and Engineering Department, University of California, San Diego, La Jolla, CA 92093; Design, Automation and Test in Europe Conference and Exhibition (Date '04), vol. 2, pp. 1290-1295 (6 pages), Feb. 2004; © 2004.
“Broadcasting Test Patterns of Multiple Circuits,” by Kuen-Jong Lee, Jih-Jeen Chen, and Cheng-Hua Huang; IEEE Transactions on Computer-Aided Design (TCAD) of Integrated Circuits and Systems, vol. 18, No. 12, pp. 1793-1802; Dec. 1999; © 1999.
“Reducing Test Application Time for Full Scan Embedded Cores,” by Ilker Hamzaoglu and Janak H. Patel; Center for Reliable & High-Performance Computing, University of Illinois, Urbana, IL 61801; IEEE International Symposium on Fault Tolerant Computing (FTC '99), pp. 260-267 (8 pages), 1999.
“BIST-Aided Scan Test—A New Method for Test Cost Reduction,” by Takahisa Hiraide, Kwame Osei Boateng, Hideaki Konishi, Koichi Itaya, Michiaki Emori, Hitoshi Yamanaka, Takashi Mochiyama; Fujitsu Laboratories Ltd.; IEEE VLSI Test Symposium (VTS '03), pp. 359-364 (6 pages), Apr. 2003, © 2003.
“A Token Scan Architecture for Low Power Testing,” by Tsung-Chu Huang and Kuen-Jong Lee; Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan 70101, R.O.C.; International Test Conference (ITC '01); pp. 660-669; Oct. 2001; © 2001.
“Test Data Compression,” by Edward J. McCluskey, Dwayne Burek, Bernd Koenemann, Subhasish Mitra, Janak Patel, Janusz Rajski, and John Waicukauski; ITC 2002 Roundtable; Design & Test of Computers, vol. 20, No. 2, pp. 76-87, Mar.-Apr. 2003; © 2003.
“Embedded Deterministic Test,” by Janusz Rajski, Jerzy Tyszer, Mark Kassab, and Nilanjan Mukherjee; IEEE Transactions on Computer-Aided Design (TCAD) of Integrated Circuits and Systems, vol. 23, No. 5, pp. 776-792, May 2004; © 2004.
“Scan Architecture with Mutually Exclusive Scan Segment Activation for Shift- and Capture-Power Reduction,” by Paul Rosinger, Bashir M. Al-Hashimi, and Nicola Nicolici; IEEE Transactions on Computer-Aided Design (TCAD) of Integrated Circuits and Systems, vol. 23, No. 7, pp. 1142-1153, Jul. 2004, © 2004.
“A Reconfigurable Shared Scan-in Architecture,” by Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, and T.W. Williams; VLSI Test Symposium (VTS '03), Apr. 2003; 6 pages; © 2003.
“Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture,” by Shervin Sharifi, Mohammad Hosseinabadi, Pedram Riahi and Zainalabedin Navabi; Electrical and Computer Engineering, University of Tehran; 14399 Tehran, Iran, and Northeastern University, Boston, Massachusetts 02115; International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT '03); 9 pages, © 2003.
“A Novel Scan Architecture for Power-Efficient, Rapid Test,” by Ozgur Sinanoglu and Alex Orailoglu; Computer Science and Engineering Department, University of California, San Diego, La Jolla, CA 92093; International Conference on Computer-Aided Design (ICCAD '02), pp. 299-303, Nov. 2002; © 2002.
“Test Cost Reduction Through a Reconfigurable Scan Architecture,” by Baris Arslan and Alex Orailoglu, Computer Science and Engineering Department, University of California, San Diego, La Jolla, CA 92093; ITC International Test Conference, Paper 33.4, pp. 945-952; Nov. 2004; © 2004.
“Random Access Scan: A Solution to Test Power, Test Data Volume and Test Time,” by Dong Hyun Baik, Kewal K. Saluja, and Seiji Kajihara, University of Wisconsin-Madison, Department of Electrical and Computer Engineering, Madison, WI 53706 and Kyushiu Institue of Tech., Department of Computer Sciences and Electronics, Iizuka 820-8502 Japan; Proceedings of the 17thInternational Conference on VLSI Design (VLSID'04); pp. 883-888, Jan. 2004; © 2004.
“Minimizing Power Consumption in Scan Testing: Patter Generation and DFT Techniques,” by Kenneth M. Butler, Jayashree Saxena, Tony Fryars, Graham Hetherington, Atul Jain, and Jack Lewis, Texas Instruments Inc., Dallas, TX 75243; ITC International Test Conference; pp. 355-364, Nov. 2004; © 2004.
“Logic BIST with Scan Chain Segmentation,” by Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng; Coordinate Science Laboratory, University of Illinois at Urbana-Champaign, 1308 West Main Street, Urbana, IL 61801-2307, and Mentor Graphics Corp., 8005 S. W. Boeckman Road, Wilsonville, OR 97070-7777; ITC International Test Conference; pp. 57-66, Nov. 2004; © 2004.
Alvamani Ahmad A.
Devta-Prasanna Narendra
Gunda Arun
Kerveros James C
LSI Logic Corporation
Suiter Swantz pc llo
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