Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-17
2001-08-14
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S294000, C438S595000
Reexamination Certificate
active
06274450
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is in the field of integrated circuits, and is more specifically directed to fabrication of metal oxide semiconductor field effect transistor that comprises ultra-shallow junction.
2. Description of the Prior Art
Metal oxide semiconductor field effect transistor (MOSFET) is generally used in contemporary electronic products. These advantages of field effect transistor comprise lower temperature formation of the metal-semiconductor barrier, low resistance along the channel width and good heat dissipation for power devices.
The conventional fabrication of MOSFET is described in following paragraph, herein a flow sheeting is disclosed in FIG.
1
. First, as first block
11
shows, provide a substrate that as usual the substrate comprises a plurality of structures in and on it, such as isolations and wells. Second, as second block
12
shows, form gate, source drain extension (SDE) and halo in and on the substrate. Third, as third block
13
shows, form spacer, source and drain in and on the substrate. Finally, as block
14
shows, form salicade on source, drain and gate, and then cover the substrate by a dielectric layer. Where function of SDE is similar to function of lightly doped drain but density of SDE is higher than lightly doped drain, and conductivity type of halo is opposite to conductivity type of SDE and halo is used to prevent short channel effect. Of course, salicade is used to provide contact window and can be replaced by other device.
Thus, structure of MOSFET comprises source, drain, gate, spacer and lightly doped drain (or called as SDE). Beside, as scale of MOSFET is decreased, in order to match the size of source/drain and size of gate, shallow junction is broadly used. Herein, function of shallow junction is to reduce resistance and scale of source and drain.
On the other hand, owing to the fact that quality of MOSFET is limited by available technology of related fabrication, naturally as scale of MOSFET is decreased then some disadvantages are appeared for each fabricating technology can only be suitable for a specific scale. For example, quality of shallow junction is degraded by following thermal processes of formation of MOSFET, and the degradation is more serious when thickness of shallow junction is further decreased.
Moreover, ultra-shallow junction is generally used as width of gate is less than about 0.25 microns, and a typical thickness of ultra-shallow junction is about 200 angstroms to 500 angstroms. Therefore, many following process of formation of MOSFET will induce serious disadvantages and let ultra-junction be degraded, no matter it is a depositing process, an annealing process or even an etching process.
For example, owing to the fact that thermal processes will increase diffusion coefficient of doped particles and then doped particles inside source and drain will significantly diffuse out source and drain, the effective length of channel is shorten by diffused doped particles and induces serious short channel effect. Thus, the source drain resistance will be increased.
Beside, according to previous introduction, it is crystal-clear that both SDE and halo are formed before spacer, source, drain and salicide, and then qualities of both halo and SDE are affected by following forming process of MOSFET. For example, the smaller thickness of shallow junction obviously increases the probability that doped particles diffuse across the margin of shallow junction.
Thus, it is desired to develop a new fabrication of the metal oxide semiconductor field effect transistor to overcome these disadvantages of conventional fabrication. And it is more important when gate width of the MOSFET is less than 0.25 microns and ultra-shallow junction is required.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method for manufacturing a metal oxide semiconductor field effect transistor.
It is another object of the invention to provide such a method that implement an MOSFET with ultra-shallow junction and low source drain resistance.
It is a further object of the invention to provide a manufacturable fabrication of MOSFET.
It is still a further object of the invention to provide a method to decrease the RC delay time of MOSFET.
In order to explain the invention that relates to a method of manufacturing metal oxide semiconductor transistor, a specific fabricating process that efficiently prevent many disadvantages of conventional fabrication of MOSFET is presented as an embodiment.
The content of the embodiment is described as following: First, a substrate is provided. Second, an isolation and a well are formed in the substrate, and then a first dielectric layer, a conductive layer and an anti-reflection coating layer are formed on the substrate in sequence. Third, a gate is formed on the substrate, and then a source and a drain are formed in the substrate and a spacer is formed on the substrate. Fourth, both source and drain are annealed, and then a first salicide is formed on both source and drain. Fifth, a second dielectric layer is formed on the substrate and is planarized, where the anti-reflecting coating layer is totally removed and the spacer is partially exposed. Sixth, a second salicide is formed on the conductive layer. Seventh, the spacer is removed and then both a halo and a source drain extension are formed in substrate. Finally, a third dielectric layer is formed on second dielectric layer.
Obviously, in the invention, both source drain extension and halo are formed after a plurality of thermal processes such as deposition, annealing and formation of salicide. By the way, both SOE and halo are not degraded by these thermal processes.
Summary, the main characteristic of the invention is both source drain extension and halo are formed after a plurality of thermal processes such as deposition, annealing and formation of salicide. Then doped particles inside both SDE and halo will not thermally diffuse across margin of both SDE and halo, and salicide on source and drain will not be diffused by thermal processes.
REFERENCES:
patent: 5162884 (1992-11-01), Liou et al.
Chen Coming
Chou Jih-Wen
Lin Tony
Estrada Michelle
Fourson George
United Microelectronics Corp.
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