Method for implementing a four-way least recently used (LRU) mec

Details Method for implementing a four-way least recently used (LRU) mec Method for implementing a four-way least recently used (LRU) mec

1996-04-29

1998-06-09

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711144, G06F 1212

Patent

active

057651914

ABSTRACT:
A method for implementing a four-way least recently used cache line replacement scheme in a four-way cache memory is disclosed. The cache memory includes multiple cache lines, and each cache line includes four congruence sets. In accordance with the present disclosure, a 5-bit Least Recently Used (LRU) field is associated with each of the cache lines within the cache memory. For a particular cache line, a set number of a least recently used set among the four congruence sets is stored in any two bits of the LRU field associated with that cache line. Next, a set number of the second least recently used set among the four congruence sets is stored in another two bits of the same LRU field associated with the same cache line. Finally, a last bit of the 5-bit LRU field is set to a specific state in response to a determination of which one of the remaining two sets is the second most recently used set.

REFERENCES:
patent: 4607331 (1986-08-01), Goodrich, Jr. et al.
patent: 5638531 (1997-06-01), Crump et al.

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