Method for identifying SMP bus transfer errors

Details Method for identifying SMP bus transfer errors Method for identifying SMP bus transfer errors

1997-10-02

2000-04-25

Palys, Joseph E.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714 12, G06F 1100

Patent

active

060556609

ABSTRACT:
In an SMP computer system where data is partitioned across one or more chips a circuit and method permits detecting errors across chip boundaries due to a control error even though the ECC is not bad. A Multiple-input Shift-Register (MISR) on each bus is used to collect a dynamic signature representing all the critical buses on each chip that need to be compared. The MISR state combines present and previous states of these buses, so the MISR will be different if one or more bus controls break. Since an N-bit MISR shifts, comparing a single bit of the MISR each cycle guarantees detection within N cycles of a problem. The method of identifying errors includes accumulating bus signature information which is a function of current and previous values of an input bus and then comparing portions of the signatures of two or more input bus structures to determine sync of buses. Part of the signature is wrapped around into the signature to cause past information to be maintained indefinitely. Additional logic is introduced, including mask logic, programmable feedback, and counters along with a method of isolating defects using these features.

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