Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-12-30
2002-05-21
Sherry, Michael J. (Department: 2829)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
Reexamination Certificate
active
06391666
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for identifying defective elements in array molding of semiconductor packaging, and more particularly to a method for identifying defective elements in array molding of semiconductor packaging of mini ball grid array (BGA) type.
2. Description of Related Art
In light of the trend of “Light, Thin, Short, and Small” of electronic products, in only a decade, the chip packaging technology of semiconductors has developed from the “Insertion Mount” type in the 1980s to the “Chip Scale Package (CSP)” technology of today. The “Insertion Mount” type of chip packages simply mounts the chip on the Print Circuit Board (PCB) while the “Chip Scale Packages (CSP)” have high density of electronic devices and are also three-dimensional instead of two-dimensional such as those that were made previously.
Following the development in the packaging technology of ultra-fine-pitch, the chip packaging technology performed by the use of the lead frame can not satisfy the requirements of this new trend anymore. And the ball grid array (BGA) package with its dominant advantages has imperceptibly become the main stream of packaging type nowadays, the mini BGA type of packaging is one of the examples.
The so called mini BGA type of package is a package that is fabricated by first forming a plurality of package sites in array, then forming electrical connections between the dies and the package sites respectively, and thereafter using a molding compound to protect the die. In this way, the dies can electrically exit out to undertake signal transmission through the connecting points formed in ball shape on the package sites and disposed in array.
FIG. 1
is a schematic top view of a mini BGA packaging substrate according to the prior art. As shown in
FIG. 1
, a common mini BGA packaging is first to form a plurality of package sites
104
, which is disposed in array, in the circuit zone
102
of the mini BGA packaging substrate
100
. Next, a plurality of dies is electrically connected to the package sites
104
respectively, then a molding process is performed to encase the whole area of the circuit zone
102
to protect the dies and bond wires by a molding compound. Thereafter, all one has to do is to saw the overall package into package sites
104
along the borderlines of the array to complete the mini BGA packaging process.
An inspection process is performed after the package sites
104
are formed in array on the mini BGA packaging substrate
100
and before the plurality of dies is electrically connected to each of the package sites
104
respectively in accordance with the foregoing statement. The purpose of the inspection is to judge initially if there are any defective package sites
104
, in the meantime, to mark them in order to differentiate them from the good ones. The way of doing this is to put an “X” mark on those defective package sites such as
104
a
in FIG.
1
.
However, the mark put on some of the package sites
104
, which are initially judged as defective ones, will be covered by the molding compound after the processes of die bonding and array molding are completed. Consequently, the defective elements can not be identified.
In the light of the foregoing disadvantage that the conventional array molding is unable to identify the defective elements after the array molding is completed, the present invention provides an identification method for identifying the defective elements.
SUMMARY OF THE INVENTION
The present invention provides a method for identifying defective elements in array molding of semiconductor packaging. The method is first to provide a mini BGA packaging substrate. Next, it provides a circuit zone on the mini BGA packaging substrate wherein a plurality of package sites disposed in array are formed in the circuit zone. Then, a plurality of marks representing the locations of each of the package sites are formed in the periphery zone other than the circuit zone on the mini BGA packaging substrate. Thereafter, it performs an inspection process to those package sites in order to find out the defective elements in the package sites. Then, it puts a symbol at those marks in the periphery zone wherein the symbol put at the marks represents the location of defective elements in the package sites. It then performs electrical connection between a plurality of dies and the package sites respectively. Finally, it performs an array molding process by the use of a molding compound to cover the dies and the package sites but not to cover the periphery zone. Therefore, one can identify the locations of the defective elements in the package sites.
The present invention also provides a method for identifying defective elements in array molding of semiconductor packaging. The method is first to provide a mini BGA packaging substrate. Next, it provides a circuit zone on the mini BGA packaging substrate wherein a plurality of package sites disposed in array are formed in the circuit zone. Then, a plurality of marks representing the locations of each of the package sites is formed in the periphery zone. Thereafter, an inspection process is performed to those package sites in order to find out the defective elements in the package sites. Then, the locations of defective elements of the package sites are recorded in an electronic file so that the locations of the defective elements in the package sites can be identified at any time. Then electrical connection is formed between a plurality of dies and the package sites respectively. Finally, an array molding process is performed by the use of a molding compound to cover the dies and the package sites. In this way, the locations of defective elements in the package sites can be identified from the electronic files.
REFERENCES:
patent: 5923959 (1999-07-01), Mess
patent: 5985680 (1999-11-01), Singhal et al.
patent: 6048755 (2000-04-01), Jiang et al.
patent: 6122562 (2000-09-01), Kinney et al.
patent: 6182883 (2001-02-01), Nikmanesh
Her Tzong-Dar
Huang Ya-Hui
Liao Chih-Chin
Geyer Scott B.
J.C. Patents
Sherry Michael J.
Siliconware Precision Industries Co. Ltd.
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