Method for identification of faulty or weak functional logic...

Details Method for identification of faulty or weak functional logic... Method for identification of faulty or weak functional logic...

2005-03-01

2005-03-01

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06862721

ABSTRACT:
A method for testing a circuit is provided. The method includes providing a normal internal clock signal for use in accessing functional logic, where the functional logic has access to redundant functional logic during normal operation. The method then applies a stress clock signal to the functional logic, and each pulse of the stress clock signal is of a shorter duration than each pulse of the normal internal clock signal. Based on the applied stress clock signal, the method identifies logic elements of the functional logic that fail to operate as intended.

REFERENCES:
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patent: 5712584 (1998-01-01), McClure
patent: 5828258 (1998-10-01), Ooishi et al.
patent: 5939914 (1999-08-01), McClure
patent: 6115836 (2000-09-01), Churchill et al.
patent: 0867887 (1998-09-01), None

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