Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of...
Reexamination Certificate
2005-09-27
2005-09-27
Coleman, W. David (Department: 2891)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
C438S694000, C438S689000, C438S643000, C438S627000, C438S653000, C438S618000
Reexamination Certificate
active
06949472
ABSTRACT:
A novel method for depositing a barrier layer on a single damascene, dual damascene or other contact opening structure. The method eliminates the need for pre-cleaning argon ion bombardment of the structure, thereby reducing or eliminating damage to the surface of the underlying conductive layer and sputtering of copper particles to the via or other contact opening sidewall. The process includes fabrication of a single damascene, dual damascene or other contact opening structure on a substrate; optionally pre-cleaning the structure typically using nitrogen or hydrogen plasma; depositing a thin metal barrier layer on the sidewalls and bottom of the structure; and redistributing or re-sputtering the barrier layer on the bottom and sidewalls of the structure.
REFERENCES:
patent: 6333255 (2001-12-01), Sekiguchi
patent: 6797642 (2004-09-01), Chu et al.
patent: 2002/0090822 (2002-07-01), Jiang et al.
patent: 2003/0129827 (2003-07-01), Lee et al.
patent: 2004/0067308 (2004-04-01), Zheng et al.
Hsieh Ching-Hua
Huang Cheng-Lin
Shue Shau-Lin
Coleman W. David
Taiwan Semiconductor Manufacturing Co. LTD
Tung & Associates
Yevsikov Victor V.
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