Semiconductor device manufacturing: process – Radiation or energy treatment modifying properties of...
Reexamination Certificate
1998-10-23
2003-03-11
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Radiation or energy treatment modifying properties of...
C438S004000, C438S974000
Reexamination Certificate
active
06531416
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for the heat treatment of a silicon wafer, and particularly to a method for the heat treatment of a silicon wafer capable of reducing crystal originated particle (hereinafter referred to as COP) density on the surface of the silicon wafer and suppressing the generation of slip dislocation.
2. Description of the Related Art
In order to improve the electrical characteristics of a silicon wafer, such as time-zero dielectric-breakdown (hereinafter referred to as TZDB), a surface layer of the silicon wafer, on which devices are fabricated, must be free of defects. Crystal defects having a regular octahedral structure, called COPs, which are introduced into the silicon single-crystal during crystal growth, are present on the surface layer of the silicon wafer, so that the electrical characteristics of the silicon wafer are degraded.
In order to improve TZDB, hydrogen annealing is said to be effective in many reports (for example, Japanese Patent Publication (kokoku) No. 5-18254 and Japanese Patent Application Laid-Open (kokai) No. 6-295912). In hydrogen annealing, a silicon wafer is treated at high temperature for several hours in a hydrogen-gas atmosphere.
In order to improve the heat treatment performance; for example, to shorten the heat-treatment time, there is proposed a heat-treatment method using a rapid thermal annealer (hereinafter referred to as RTA). For example, Japanese Patent Application Laid-Open (kokai) No. 7-161707 proposes a method for improving TZDB through a heat treatment performed at a relatively low temperature of 950° C. to 1200° C. for a short time of 1 sec to 60 sec.
However, in the conventional heat treatment as disclosed in Japanese Patent Application Laid-Open No. 7-161707, heat treatment conditions are determined in view of TZDB. Also, in the embodiment described in the publication, although bulk micro defect (hereinafter referred to as BMD) density is taken into account, COPs present on the wafer surface is not considered. Such COPs directly affect electrical characteristics of devices.
The inventors of the present invention experimentally studied the above conventional heat treatment method and found that the conventional method somewhat improves TZDB, but fails to exhibit a satisfactory effect of improving COP density. In other words, the conventional heat treatment method is not very effective for improvement of electrical characteristics of a silicon wafer except for TZDB. Specifically, even when, for example, a silicon wafer is subjected to hydrogen annealing at 1050° C. for 30 sec as proposed in the conventional heat treatment method, COP density does not decrease, and in some case haze level indicative of surface roughness rather worsens due to etching of silicon by hydrogen. Also, hydrogen annealing even at 1100° C. is not satisfactorily effective for elimination of COPs. Thus, the conventional heat treatment conditions are not satisfactorily effective for an improvement of the COP density.
To cope with the above problems, the inventors of the present invention proposed, in Japanese Patent Application No. 9-92952, a method for the heat treatment of a silicon wafer in a reducing atmosphere using an RTA, particularly a method for the heat treatment of a silicon wafer capable of reducing COP density on the surface of the silicon wafer.
According to the proposed method, a silicon wafer is treated at a temperature of 1200° C. to the melting point of silicon for 1 sec to 60 sec in a reducing atmosphere. Preferably, the reducing atmosphere is a 100% hydrogen atmosphere or a mixture gas atmosphere of hydrogen and argon, and the heat treatment time is 1 sec to 30 sec.
It was proved that the proposed method significantly decreases the COP density on the silicon wafer surface and significantly improves the electrical characteristics, such as TZDB and time dependent dielectric breakdown (hereinafter referred to as TDDB). Also, the inventors of the present invention confirmed that even when a device-fabrication process includes an oxidizing heat-treatment, which tends to generate COPs on the wafer surface, COPs are less likely to be generated as compared to the case of a silicon wafer heat-treated by the conventional method. That is, the proposed method suppresses the generation of COPs and enables fabricated devices to retain good electrical characteristics. Further, use of an RTA prevents occurrence of oxygen precipitation, which would otherwise occur in heat treatment, and suppresses the occurrence of wafer warp.
As a result of subsequent studies on hydrogen annealing, the inventors of the present invention confirmed that the conditions of the heat treatment in a reducing atmosphere as described in Japanese Patent Application Laid-Open (kokai) No. 7-161707 not only fail to sufficiently decrease COP density but also cause a temperature difference in the wafer surface, a tendency peculiar to an RTA, resulting in a strong likelihood of generation of slip dislocations.
Also, it has been found that the conditions for the heat treatment in a reducing atmosphere as described in Japanese Patent Application No. 9-92952 significantly decreases COP density and thereby significantly improves electrical characteristics, such as TZDB and TDDB, of a silicon wafer; and that the heat treatment method of the publication, however, is not necessarily free from the generation of slip dislocation. That is, the heat treatment method can decrease COP density, but in some case causes the generation of slip dislocation.
Since a silicon wafer suffering the generation of slip dislocations breaks during a device-fabrication process and has an adverse effect on the electrical characteristics of fabricated devices, there must be created a method for the heat treatment of a silicon wafer which is not accompanied by the generation of slip dislocations.
SUMMARY OF THE INVENTION
The present invention has been accomplished to solve the above-mentioned problems, and an object of the invention is to provide a method for the heat treatment of a silicon wafer in a reducing atmosphere using an RTA, which method decreases COP density on the surface of the silicon wafer to thereby improve the electrical characteristics, such as TZDB and TDDB, of the silicon wafer, suppresses the generation of slip dislocations to thereby prevent wafer breakage, and utilizes intrinsic advantages of the RTA, such as improvement in productivity and reduction in hydrogen gas usage.
To achieve the above object, the present invention provides a method for the heat treatment of a silicon wafer, in which a silicon wafer is heat-treated in a reducing atmosphere through use of a rapid thermal annealer (RTA). In the method, the silicon wafer is heat-treated at a temperature of 1150° C. to 1300° C. for 1 sec to 60 sec in a reducing atmosphere, which is a mixture gas atmosphere of hydrogen and argon in which hydrogen is present in an amount of 10% to 80% by volume.
The rapid thermal annealing can be performed by a method in which a wafer is rapidly placed into a heat treatment furnace whose temperature is maintained within the above temperature range, and, immediately after the elapse of the above heat treatment time, the wafer is rapidly taken out from the furnace, or a method in which a silicon wafer is brought to a predetermined position within a heat treatment furnace and is then rapidly heated by a heater such as a lamp heater. The description “a wafer is rapidly placed into a heat treatment furnace and is rapidly taken out from the furnace after heat treatment” means that the wafer is placed into the heat treatment furnace and taken out from the furnace, without performing conventional control in which the temperature of a heat treatment furnace is increased and decreased over a predetermined time, or in which the silicon wafer is slowly loaded into and unloaded from the heat treatment furnace. Of course, transferring the wafer to a predetermined position within a furnace takes a certain time, which ranges from several secon
Kobayashi Norihiro
Miyano Toshihiko
Oka Satoshi
Fahmy Wael
Hogan & Hartson LLP
Pizarro-Crespo Marcos D.
Shin-Etsu Handotai & Co., Ltd.
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