Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
Reexamination Certificate
2001-01-23
2004-03-16
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Data formatting to improve error detection correction...
C714S718000
Reexamination Certificate
active
06708298
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to integrated circuits. In particular, the present invention relates to a method for testing memory devices such as Double Data Rate (DDR) memory devices.
BACKGROUND OF THE INVENTION
In synchronous semiconductor memory devices of the single-data rate (SDR) type, data is latched at the rising edge of the clock (CLK) signal. In synchronous semiconductor memory devices of DDR type, however, a timing circuit is provided that not only latches data at the rising edge of the clock (CLK) signal, but also at the trailing edge thereof, i.e., the middle of the cycle of the clock (CLK) signal. Accordingly, in a DDR-type memory device, twice as much data can be transferred within a unit time as compared to an SDR-type memory device. A timing diagram illustrating the general timing differences between SDR and DDR-type memory devices is provided in FIG.
1
. As illustrated in
FIG. 1
, for DDR-type memory devices, output data is provided on the data Input/Output, or “DQ” lines, in response to a Data Strobe (DQS) pulse or window.
The width tDSQ of the data strobe (DQS) valid window and the width tDV of the data valid window are critical factors in the implementation of DDR memory systems. These factors must be characterized in development and guaranteed during manufacturing testing. Unfortunately, known techniques for establishing the widths of the data strobe valid window and the data valid window result in poor yield or tighter specifications than necessary, since these parameters cannot be tested directly using currently available methods. For example, current industry standards limit the minimum width of the data valid window tDV to 0.35*tCK (clock duty cycle). This corresponds to 2.625 nS for PC266 DDR memory (tCK=7.5 ns). Current industry standards also limit tDQSCK
max/min
(data strobe (DQS) to data (DQ) skew) to 500 pS for PC266 DDR memory.
A need exists, therefore, for a method for more accurately determining the widest possible minimum data strobe valid window and data valid window that can be guaranteed on a cycle to cycle basis.
SUMMARY OF THE INVENTION
The present invention provides a method for determining a wider data strobe (DQS) valid window that is guaranteed on a cycle to cycle basis. In addition, the present invention provides a method for determining a wider data valid window (tDV) that is also guaranteed on a cycle to cycle basis.
Generally, the present invention provides a method, comprising:
providing a memory device;
providing a testing system having a window strobe; and
using the window strobe of the testing system to determine a width of a signal window of the memory device.
The present invention also provides a method for testing a data strobe window (DQS) of a memory device, comprising:
providing a testing system having a window strobe; and
determining a valid width of DQS using the window strobe.
The present invention further provides a method for testing a data valid window (tDV) of a memory device, comprising:
providing a testing system having a window strobe; and
determining a valid width of tDV using the window strobe.
The foregoing and other features of the invention will be apparent from the following more particular description of the embodiments of the invention.
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Chapman David E.
Corbin, Jr. William E.
Fiscus Timothy E.
Monty David P.
Nelson Erik A.
Chaudry Mujtaba
De'cady Albert
International Business Machines - Corporation
Schmeiser Olsen & Watts
Walsh Robert A.
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