Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2001-10-12
2004-10-12
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S765000, C438S769000, C438S775000, C438S786000, C438S787000
Reexamination Certificate
active
06803330
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates, in general, to a process for fabricating integrated circuit devices in which a layer of an oxynitride material is formed and, in particular, to a method of nitriding a gate oxide layer using nitric oxide (NO) gas.
2. Background of the Technology
Semiconductor devices such as MOS (metal-oxide-semiconductor) devices are typically formed on a substrate such as a silicon wafer. Typically, one or more films of an insulating material such as silicon dioxide are formed on the substrate over which is formed a gate electrode. The insulating film formed between the gate electrode and the silicon substrate is referred to as the gate oxide or gate dielectric. A widely employed type of MOS integrated circuit is a metal-oxide-semiconductor field-effect transistor, or MOSFET.
Boron doping of the gate electrodes of MOS devices (e.g., p
+
gates) has been used to improve device performance by reducing short-channel effects and lowering threshold voltages. Typically, boron is implanted into the poly-Si gate at sufficiently high concentrations to ensure adequate conductance of the poly-Si gate. With the continued push for smaller and smaller MOSFET dimensions, however, higher active dopant concentrations are required. When boron is used as the dopant for p
+
gates, boron atoms in the gate layer can diffuse into the gate dielectric during downstream processing. Boron, which is a relatively small atom, has a very high diffusion coefficient in both silicon and silicon dioxide at temperatures encountered during processing. Further, it is necessary to activate the boron dopant after implantation with a high-temperature anneal which is typically conducted at temperatures in the range of 950-1050° C. During this high-temperature anneal, boron diffusion can be exacerbated.
Boron penetration into and through the gate dielectric can also have significant effects on device characteristics. First, boron penetration through the gate dielectric and into the channel can influence device performance. Boron diffusion into the channel, for example, can result in a shift in the threshold voltage of the device and can even result in charge-induced damage and breakdown during device operation. Also, as boron penetrates into the gate dielectric layer, the capacitance-voltage (C-V) or flat-band voltage of the device can shift which can degrade device performance. The presence of boron in the gate oxide film can also degrade the quality of the gate oxide film.
The reduction of boron penetration is particularly important in light of the decreasing dielectric layer thicknesses of modem MOS devices. It is known to incorporate nitrogen into an oxide film to retard the effects of boron penetration Nitrogen is believed to block boron diffusion by forming B-N complexes.
The amount of nitrogen incorporated into the gate oxide generally determines the effectiveness of the oxide layer in blocking boron diffusion. The amount of nitrogen doping required in a particular application, however, is dictated in part by the thermal cycles to which the device is subjected after deposition and doping of the gate electrode. Typical amounts of nitrogen required for adequate levels of boron diffusion blocking are in the range of 1 to 3 at %.
Nitrogen has been incorporated into SiO
2
using various methods. These methods include thermal oxidation followed by annealing in a nitrogen containing environment (thermal nitridation) and various deposition techniques such as physical vapor deposition (PVD) and chemical vapor deposition (CVD).
Various nitrogen containing gases have been employed for thermal nitridation and oxy-nitride deposition, including N
2
, NH
3
, NO and N
2
O. See, for example, U.S. Pat. Nos. 5,403,786; 5,521,127; 5,629,221; and 5,880,040. See also Gusev, et al., “Growth and Characterization of Ultrathin Nitrided Silicon Oxide Films”, in IBM J. Res. Develop., Vol. 43, No. 3, May 1999, pp. 265-286; Hook, et al., “Nitrided Gate Oxides for 3.3-V Logic Application: Reliability and Device Design Considerations”, in IBM J. Res. Develop., Vol. 43, No. 3, May 1999, pp. 393-406; and Buchanan, “Scaling the Gate Dielectric: Materials, Integration and Reliability”, in IBM J. Res. Develop., Vol. 43, No. 3, May 1999, pp. 245-264. Evans, et al. disclose a high pressure (15 to 25 atm.) process for oxynitride gate formation using nitric oxide gas. gas. See Evans, et al., “High Performance CMOS Devices with 20 Å Engineered Oxynitride Gate Dielectrics”, Paper Presented at Semicon Korea Technical Symposium, February 2000).
Conventional nitridation methods, however, generally result in a relatively low concentration of nitrogen in the films. For example, oxide films that were either grown or annealed in N
2
O typically have total integrated nitrogen concentrations of less than 1 at. %. While these relatively low concentrations of nitrogen may be sufficient for controlling channel hot-electron degradation effects in MOSFETs, they are usually insufficient to reduce the effects of boron penetration from a p
+
poly-Si gate into and through the gate dielectric layer. In order to incorporate sufficient amounts of nitrogen in the gate oxide layer, annealing has typically been conducted at relatively high temperatures (e.g., 900° C. and greater) and/or relatively high pressures well in excess of atmospheric pressure.
The use of a CVD furnace has been found to produce relatively thin oxide layers having high uniformity due in part to the low oxidation rates that can be achieved in a CVD furnace. CVD furnaces, however, are designed to operate at atmospheric or sub-atmospheric pressures and are typically not designed to exceed about 800° C. The extreme annealing temperatures and pressures required to achieve adequate gate nitridation with conventional nitridation processes thus preclude the use of a CVD furnace to perform nitridation using a nitrous oxide anneal. Also, CVD races can not be easily adapted for use with torches conventionally used for preheating nitridation gases such as N
2
O.
There still exists a need for a nitridation process which incorporates a sufficient amount of nitrogen into the gate oxide layer at relatively low pressures and temperatures such that annealing can be conducted in a CVD furnace. Such a process would allow for in-situ nitridation in a CVD furnace after gate oxide formation.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a method of forming a gate oxide layer on a semiconductor substrate is provided. The method comprises: forming an oxide layer on the substrate by oxidizing the substrate in a CVD furnace; introducing nitric oxide (NO) gas into the CVD furnace; and nitriding the oxide layer with the nitric oxide gas in-situ . In a preferred embodiment of the aforementioned method, the oxide forming and nitriding steps are performed at approximately the same temperature. According to another preferred embodiment of the aforementioned method, the oxide forming and/or nitridation steps are performed at a pressure of about 1 atm. or less. The nitrided gate oxide layer can optionally be reoxidized in a second oxidation step after the nitridation step. A gate electrode layer can be then deposited on top of the nitrided gate oxide layer or on top of the reoxidized and nitrided gate oxide layer. In a preferred embodiment the gate electrode layer comprises a polysilicon layer or a polycrystalline silicon/germanium layer which is doped with a dopant such as boron. The gate electrode layer according to the invention can also be a stack comprising a polysilicon layer or a polycrystalline silicon/germanium layer in combination with a separate layer of material such as tungsten or tungsten silicide.
According to a second aspect of the invention, a method of nitriding a gate oxide layer on a semiconductor substrate with nitric oxide (NO) gas is provided. The nitriding step is conducted at a temperature of about 800° C. or less and at a pressure of about 1 atm or less.
REFERENCES:
patent: 5403786 (1995-04-01), Hori
p
Narayanan Sundar
Ramkumar Krishnaswamy
Cypress Semiconductor Corporation
Hogans David L.
Jr. Carl Whitehead
Kelber Steven B.
Piper Rudnick LLP
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