Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-08-18
2000-03-14
Nelms, David
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438213, 438270, 438489, H01L 218238, H01L 21336
Patent
active
060372028
ABSTRACT:
A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).
REFERENCES:
patent: 4554570 (1985-11-01), Jastrzebski et al.
patent: 4740826 (1988-04-01), Chatterjee
patent: 4757029 (1988-07-01), Koury, Jr.
patent: 4890144 (1989-12-01), Teng et al.
patent: 4974060 (1990-11-01), Ogasawara
patent: 4982266 (1991-01-01), Chatterjee
patent: 5010386 (1991-04-01), Groover, III
patent: 5110757 (1992-05-01), Arst et al.
patent: 5122848 (1992-06-01), Lee et al.
patent: 5140388 (1992-08-01), Bartelink
patent: 5158901 (1992-10-01), Kosa et al.
patent: 5285093 (1994-02-01), Lage et al.
patent: 5302846 (1994-04-01), Matsumoto
patent: 5308776 (1994-05-01), Fitch et al.
patent: 5308782 (1994-05-01), Mazure et al.
patent: 5324673 (1994-06-01), Fitch et al.
patent: 5398200 (1995-03-01), Mazure et al.
patent: 5408130 (1995-04-01), Woo et al.
"High Performance Characteristics in Trench Dual Gate MOSFET (TDMOS)," Mizuno et al; IEEE Transactions on Electron Devices, Sep. 1991.
"Impact of Surrounding Gate Transistor (SGT) for Ultra-High Density LSI's," Takato et al; IEEE Transactions on Electron Devices, vol. 38, No. 3, Mar. 1991.
Lebentritt Michael S.
Motorola Inc.
Nelms David
Witek Keith E.
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