Method for generating test signals for an integrated circuit...

Details Method for generating test signals for an integrated circuit... Method for generating test signals for an integrated circuit...

2005-03-22

2005-03-22

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S030000

Reexamination Certificate

active

06870392

ABSTRACT:
To generate test signals by a test logic unit on a semiconductor wafer, the test signals being used to check specific functions and/or parameters of an integrated circuit on the semiconductor wafer, at least two test signals are provided substantially simultaneously by the test logic unit and are subsequently serialized to generate a multiplexed test signal sequence with a data rate required for testing.

REFERENCES:
patent: 5390192 (1995-02-01), Fujieda
patent: 5517455 (1996-05-01), McClure et al.
patent: 6032282 (2000-02-01), Masuda et al.
patent: 6058057 (2000-05-01), Ochiai et al.
patent: 6605956 (2003-08-01), Farnworth et al.
Kawagoe, T. et al.: “A Built-In Self-Repair Analyzer (CRESTA) for Embedded DRAMs”, ITC International Test Conference, IEEE, Paper 21.3, 2000, pp. 567-574.

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