Method for generating test patterns

Details Method for generating test patterns Method for generating test patterns

1997-10-16

2000-04-18

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714741, G01R 3128

Patent

active

060528095

ABSTRACT:
A method for generating test patterns for testing digital electronic circuits, whereby a test pattern template is defined that fully specifies some primary inputs while other primary inputs are specified in accordance with selected series of codes. The test pattern template is then repeatedly converted into a stimulus pattern using different integers in the selected series of codes, and fault simulation is performed on a circuit under test using each stimulus pattern. A stimulus pattern is then saved for subsequent testing of the circuit under test whenever fault simulation using that stimulus pattern shows that fault coverage has increased. The method significantly reduces the number of primary input combinations required for generating test patterns.

REFERENCES:
patent: 4773028 (1988-09-01), Tallman
patent: 4860291 (1989-08-01), Damm et al.
patent: 5029171 (1991-07-01), Lee et al.
patent: 5177440 (1993-01-01), Walker, III et al.
patent: 5596587 (1997-01-01), Douglas et al.
patent: 5640403 (1997-06-01), Ishiyama et al.
patent: 5790836 (1998-08-01), Mizumo

Affiliated with

Also associated with

Rating

Method for generating test patterns does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for generating test patterns, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for generating test patterns will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2345835