Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2005-11-03
2010-02-23
Chu, Chris C (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257SE23145, C257S758000, C257S773000, C257S776000, C438S129000, C438S622000
Reexamination Certificate
active
07667332
ABSTRACT:
A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
REFERENCES:
patent: 5948573 (1999-09-01), Takahashi
patent: 6225697 (2001-05-01), Iguchi
patent: 6253362 (2001-06-01), Anand et al.
patent: 6261883 (2001-07-01), Koubuchi et al.
patent: 2001/0042921 (2001-11-01), Mori et al.
patent: 2002/0061608 (2002-05-01), Kuroda et al.
patent: 63-025952 (1988-02-01), None
patent: 04-218918 (1992-08-01), None
patent: 09-321044 (1997-12-01), None
patent: 11-297817 (1999-10-01), None
patent: 2002-134618 (2002-05-01), None
patent: 2004-88102 (2004-03-01), None
patent: WO 01/63673 (2001-08-01), None
M. Okazaki, et al., “Sea of Kelvin Multiple-pattern arrangement interconnect characterization for Low-k/Cu dual damascene and its findings”, IITC 2004, Proceedings, pp. 211-213.
Notification of Reasons for Refusal mailed by the Japanese Patent Office on Jul. 14, 2009, for Japanese Application No. P2005-321571.
Fujimaki Takeshi
Hatano Masaaki
Higashi Kazuyuki
Kaneko Hisashi
Matsunaga Noriaki
Chu Chris C
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
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