Method for generating digital communication system clock signals

Details Method for generating digital communication system clock signals Method for generating digital communication system clock signals

1994-10-31

1996-11-12

Chin, Wellington

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375375, 327147, 327149, 327156, 331 14, 331 25, H03D 324

Patent

active

055747566

ABSTRACT:
A clock generating circuit generates 2n clocks (where n is a positive integer number) each having 1/2n frequency of a maximum baud rate of data bit-stream input and a phase difference of .pi.
between successive phases thereof, and simultaneously shifts the phases on the clocks ahead or behind until the phases between the clocks and corresponding data bits of the data bit-stream input are locked in quadrature, by comparing the phase of the clock with those of data bit-stream input and adjusting the phases of the clocks.

REFERENCES:
patent: 4494021 (1985-01-01), Bell et al.
patent: 4584695 (1986-04-01), Wong et al.
patent: 4821297 (1989-04-01), Bergmann et al.
patent: 5132633 (1992-07-01), Wong et al.
patent: 5185768 (1993-02-01), Ferraiolo et al.
patent: 5239561 (1993-08-01), Wong et al.
patent: 5245637 (1993-09-01), Gersbach et al.

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