Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-04-24
2000-06-20
Cady, Albert De
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
G01R 3128
Patent
active
060790385
ABSTRACT:
A method of operating an integrated circuit (IC) tester is disclosed in which an IC is repeatedly tested with respect to a limited number of combinations of values of two variable IC operating parameters (X and Y) to determine the boundary of a two-dimensional range of combinations of values of the X and Y parameters for which the IC passes a test. After finding a combination of X and Y parameter values on the boundary, each combination of parameter values to be tested thereafter is selected by altering either the X or Y parameter value, with the decision based on whether the IC passed the last test and on the manner in which a last tested combination of X and Y parameter values was selected.
REFERENCES:
Niewczas, Maly, Strojwas. "A Pattern Matching Algorithm for Verification and Analysis of Very Large IC Layouts", in Proc. of International Symposiumon on Physical Design, Monterey, CA. pp. 129-134, Apr. 1998.
Baker, Van Beers. "Shmoo plotting: the black art of IC testing", IEEE Design & Test of Computers. pp. 90-97, Jul. 1997.
Hamada, Kumanoya, Ishii, Kawagoe, Niiro. "A high-speed boundary search Shmoo plot for ULSI memories", Records of the 1993 IEEE International Workship on Memory Testing. pp. 4-9, Aug. 1993.
Hickling. "Extending binary searches to two and three dimensions (IC testing)", Proceedings of the 1990 International Test Conference. pp. 721-725, Sep. 1990.
Bedell Daniel J.
Huston Robert
Bedell Daniel J.
Cady Albert De
Credence Systems Corporation
Lin Samuel
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