Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-06-26
2004-09-07
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S445000
Reexamination Certificate
active
06787426
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to, a method for forming word line of semiconductor device, and more specifically, to a method for forming word line of semiconductor device wherein a lower portion of the word line on the channel region is a I-type and a upper portion of the word line is a line-type for improved characteristics, yield and reliability of the device.
2. Description of the Prior Art
FIG. 1
is a layout view of a conventional word line, and
FIG. 2
is a cross-sectional view taken along the line I—I of FIG.
1
.
Referring to
FIGS. 1 and 2
, gate electrodes
17
having gate oxide films
15
disposed on a p-type semiconductor substrate
11
having device isolation films
13
defining active regions
12
, and source/drain regions
19
disposed on the semiconductor substrate
11
at both sides of the gate electrode
17
are illustrated.
The active regions
12
are spaced apart by a predetermined distance from one another in horizontal direction, and alternately arranged in vertical direction. Word lines which are the line-type gate electrodes
17
are spaced apart by a predetermined distance in horizontal direction, and cross the active region
12
at two points.
Since the gate electrode
17
is line-type gate electrode, the gate electrode
17
overlaps an end portion of the active region
12
shown as ‘A’ in
FIG. 1
, as well as the two point where the gate electrode
17
cross the active region
12
. The overlapping generates Gate Induced Drain Leakage(“GIDL”) due to a voltage difference between the word line and the source/drain region, which leads to loss of charges stored in a capacitor, thereby degrading the refresh characteristics of the device.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming word line of semiconductor device wherein a lower portion of the word line on the channel region is a I-type and a upper portion of the word line is a line-type so that the overlap of the end of the active region and the word line is prevented to reduce GIDL and to improve characteristics, yield and reliability of the device.
In order to achieve the above object of the present invention, a method for forming word line of semiconductor device, comprising the steps of: (a) forming a sacrificial insulation film on a semiconductor substrate including a device isolation film defining an active region; (b) selectively etching the sacrificial insulation film to form an I-type sacrificial insulation film pattern on a predetermined region of the active region where a channel region is to be formed; (c) forming a source/drain region on the semiconductor substrate at both sides of the sacrificial insulation film pattern; (d) forming a first interlayer insulation film on the entire surface; (e) planarizing the first interlayer insulation film to expose a top surface of the sacrificial insulation film pattern; (f) sequentially forming a insulation film and a second interlayer insulation film on the entire surface; (g) etching the second interlayer insulation film and insulation film using a word line mask; (h) removing the sacrificial insulation film pattern to expose the semiconductor substrate; (i) growing a gate oxide film on the exposed portion of the semiconductor substrate; (j) forming a conductive layer on the entire surface; and (k) planarizing the conductive layer to expose the second interlayer insulation film is provided.
REFERENCES:
patent: 6159835 (2000-12-01), Visokay et al.
patent: 6406959 (2002-06-01), Prall et al.
patent: 6649453 (2003-11-01), Chen et al.
patent: 6649490 (2003-11-01), Lee et al.
patent: 6649510 (2003-11-01), Lee
patent: 6696713 (2004-02-01), Ishibashi
patent: 6710420 (2004-03-01), Dickerson et al.
patent: 6716644 (2004-04-01), Nejad et al.
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Lindsay Jr. Walter L.
Niebling John F.
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