Method for forming wire line by damascene process using hard...

Details Method for forming wire line by damascene process using hard... Method for forming wire line by damascene process using hard...

2006-05-30

2006-05-30

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S629000, C438S633000, C438S634000, C438S673000, C438S713000, C438S978000

Reexamination Certificate

active

07052952

ABSTRACT:
A method for forming a wire line by a damascene process includes forming a first insulating layer on a semiconductor substrate, etching the first insulating layer to form a contact hole, and forming a first conductive layer over the first insulating layer that fills the contact hole. The first conductive layer is patterned, and a storage node contact is formed that fills the contact hole and is electrically connected to the semiconductor substrate. A hard mask is formed over the storage node contact and the first insulating layer is etched using the hard mask as an etch mask to form a trench in the first insulating layer. A bit line is formed in the trench that is electrically connected to the semiconductor substrate. A second insulating layer is formed that covers the bit line. The second insulating layer and the hard mask are planarized and a storage node of a capacitor is formed on the storage node contact.

REFERENCES:
patent: 6274423 (2001-08-01), Prall et al.
patent: 6486018 (2002-11-01), Roberts et al.
patent: 6524907 (2003-02-01), Parekh et al.
patent: 6872622 (2005-03-01), Tu

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