Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure
Reexamination Certificate
2001-05-01
2003-07-22
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
Having specified scribe region structure
C438S619000
Reexamination Certificate
active
06596611
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for forming a wafer level package and package formed and more particularly, relates to a method for forming a wafer level package that has serpentine-shaped electrode in-between each two of a plurality of IC dies along a scribe line and package formed by such method.
BACKGROUND OF THE INVENTION
In recent years, wafer level packages or wafer level chip scale packages have been developed as a new low cost packaging technique for high volume production of IC chips. One of the chip scale packaging techniques has been developed by the Tessera Company for making a so-called micro-BGA package. The micro-BGA package can be utilized in an environment where several of the packages are arranged in close proximity on a circuit board or a substrate much like the arrangement of individual tiles. Major benefits achieved by a micro-BGA package are the combined advantages of a flip chip assembly and a surface mount package. The chip scale packages can be formed in a physical size comparable to that of an IC chip even though, unlike a conventional IC chip such as a flip chip, the chip scale package does not require a special bonding process for forming solder balls. Furthermore, a chip scale package may provide larger number of input/output terminals than that possible from a conventional quad flat package, even though a typical quad flat package is better protected mechanically from the environment.
In a typical micro-BGA package, a flexible interposer layer (which may contain circuit) is used to interconnect bond pads on an IC chip to an array of solder bump connections located on a flexible circuit. The flexible circuit, normally of a thickness of approximately 25 nm, is formed of a polymeric material such as polyimide which is laminated to a silicon elastomer layer of approximately 150 nm thick. The silicon elastomeric layer provides flexibility and compliance in all three directions for relief of stresses and thermal expansion mismatches. To further reduce the fabrication cost of IC devices, it is desirable that if a whole wafer can be passivated to seal the IC dies on the wafer, and then be severed into individual IC dies from the wafer such that not only the benefits of a chip scale package can be realized, the packaging cost for the IC dies may further be reduced.
The conventional flip-chip bonding process requires multiple preparation steps for IC chips, i.e. the formation of aluminum bond pads on the chip, the under-bump-metallurgy process on the bond pads and the deposition of solder required in the bumping process. The substrate that the IC chip is bonded to requires a flux coating in order to ensure an acceptable bond strength is formed between the solder bumps and the conductive elements on the substrate surface. The flip chip bonding process further requires a reflow process for the bumps, a flux cleaning process to eliminate excess flux material from the surface of the bump, a drying process after the cleaning process, an underfill process for dispensing an underfill material, and an underfill curing process to minimize thermal stresses in the underfill and in the joint formed.
The conventional method for depositing solder bumps described above presents a number of processing difficulties. For instance, in modern high-density semiconductor devices, the distance between I/O pads in a peripheral array continuously being reduced. In order to maintain a minimal required distance between the I/O pads, an I/O pad redistribution process must be conducted such that the pads can be transformed from a peripheral array to an area array. During the pad redistribution process, a plurality of metal traces must be formed to extend the I/O pads from the periphery of an IC die to the center of the IC die. It is desirable that, in order to assure the reliability of the die, a stress buffer layer is provided under the plurality of metal traces to buffer, or absorb, the stress incurred during the fabrication processes and to avoid stress cracking or fracture of the metal traces. The application of the stress buffering layers has been difficult in that if too thin a layer is applied, the stress buffering effect is insufficient to ensure the reliability of the IC die. However, when too thicker a layer of the stress buffering material is applied, numerous processing difficulties are incurred in the application process. Even though commercial stress buffering materials have been available in the marketplace, the fabrication technology for applying such materials to a satisfactory thickness has not been developed.
In the current technology for fabricating wafer level chip scale packages (WL-CSP), the input/output (I/O) redistribution layer and the electroplating seed layer must be deposited in separate processing steps. The two layers must be separately deposited by a sputtering technique, photolithographically exposed and developed, and then etched in different etching steps. The fabrication process requires complicated process steps resulting in a high cost fabrication process and a low fabrication yield.
Furthermore, in order to carry out an electroplating process for filling the solder bump openings formed in a photoresist layer, a common electrode must be formed in-between the plurality of IC dies to provide electrical communication with each I/O redistribution lines that also serve as an I/O redistribution pad for growing a solder bump thereon. The common electrode is conventionally laid out as a straight line in-between two IC dies along the scribe line that is latter used for severing the dies during a dicing step. The severing of IC dies from each other is normally performed by sawing with a diamond disk along a common electrode line. Any misalignment between the diamond saw blade and the common electrode line can lead to intra-die or inter-die shorting.
FIGS. 1A-1D
illustrate a conventional solder bump formation process on I/O redistribution pads. For instance,
FIG. 1A
is an enlarged, cross-sectional view of a wafer
10
that has a conductive pad
12
formed on a silicon substrate
14
and insulated by an insulating layer
16
. An I/O redistribution line
20
is formed on top of the conductive pad
12
insulated by a second insulating layer
22
with an opening
18
for an I/O redistribution pad. A metal seed layer
24
is then deposited over the top of the wafer
10
. Alternatively, an under-bump-metallurgy layer can be deposited in place of the metal seed layer
24
. This is shown in FIG.
1
B.
In the following step, as shown in
FIG. 1C
, on top of the metal seed layer
24
is deposited a thick photoresist layer
26
, a window is then opened in the photoresist layer
26
and filled with a solder bump
28
. In the final step of the process, as shown in
FIG. 1D
, the photoresist layer
26
and the metal seed layer
24
are etched away at areas not covered by the solder bump
28
. The solder bump
28
is then reflown into a solder ball
30
. The wafer
10
is then severed by a diamond saw blade
32
along a scribe line in-between the plurality of IC dies.
The conventional process shown above in
FIGS. 1A-1D
for forming solder bumps by an electroplating technique requires the pre-deposition of a metal seed layer before the plating process can be carried out. Moreover, a common electrode for electrical communication during the plating process is laid in-between the plurality of IC dies in a linear manner such that the complete severing of the electrode demands an accurate diamond sawing process. These various processing steps lead to a high cost and time consuming fabrication process. Furthermore, when an etching method is used to remove the metal seed layer under the photoresist layer, the process frequently leads to an oxidation of the solder bumps which may lead to a problematic solder reflow process. Moreover, after the solder reflow process, there is no convenient way for increasing the solder ball thickness or improving the surface characteristics of the solder balls.
It is therefore an object of the present i
Lu Ming
Lu Szu-Wei
Industrial Technology Research Institute
Lattin Christopher
Niebling John F.
Tung & Associates
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