Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Patent
1999-01-06
2000-06-27
Utech, Benjamin L.
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
438697, 438708, 438723, 438724, 438704, 438725, 438700, H01L 21302
Patent
active
060806745
ABSTRACT:
A method for forming a plurality of self-aligned via holes applied to a semiconductor device is disclosed. The method includes steps of (a) providing a substrate forming thereon a conducting layer forming thereon a sacrificial layer; (b) partially removing the sacrificial layer while retaining a plurality of sacrificial via pillars, and removing portions of the conducting layer under the removed sacrificial layer; (c) forming a first insulating layer between the plurality of the sacrificial via pillars, and then planarizing the first insulating layer to expose tops of the plurality of sacrificial via pillars; and (d) removing the plurality of the sacrificial via pillars while retaining the first insulating layer to form the plurality of the self-aligned via holes. By the above-described method, the formed via holes are self-aligned to the underlying metal lines and pads and less photolithography equipment requirement is needed to define fine via holes.
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Peng Chun-Hung
Wu Hua-Shu
Tran Binh X.
United Microelectronics Corp.
Utech Benjamin L.
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