Method for forming via-hole in semiconductor device

Details Method for forming via-hole in semiconductor device Method for forming via-hole in semiconductor device

2006-05-30

2009-08-04

Le, Thao X (Department: 2892)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S744000, C257SE21578

Reexamination Certificate

active

07569481

ABSTRACT:
Disclosed is a method for forming a via-hole for interconnection of metallization and/or metal wires in a semiconductor device. The present method may include the steps of: (a) forming an insulating layer on a semiconductor substrate including a lower metallization and/or metal wiring; (b) forming a mask (e.g., a photo-resist pattern) on the insulating layer; (c) dry etching the insulating layer using the photo-resist pattern as a mask to form a via-hole in the insulating layer; and (d) in the same dry etching chamber, etching a top portion of the insulating layer in the vicinity of the via-hole with an etchant comprising oxygen and argon.

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patent: 6642153 (2003-11-01), Chang et al.
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