Method for forming vertical transistor and trench capacitor

Details Method for forming vertical transistor and trench capacitor Method for forming vertical transistor and trench capacitor

2003-08-13

2004-10-26

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000, C438S246000, C438S249000, C438S270000, C438S386000, C438S389000, C438S392000

Reexamination Certificate

active

06808979

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor process for fabricating memory cells, and in particular to method for forming a vertical transistor and a trench capacitor.
2. Description of the Art
In the process for fabricating integrated circuits with higher integration density, size reduction for each memory cell and power consumption must be considered and optimized in order to enhance its access speed. Conventional designs for planar transistors tend to decrease the gate lengths in transistors, thus reducing lateral areas of each memory cell. However, leakage resistance of the gate is decreased and the voltage applied on the wordline must be relatively reduced. Consequently, electric charges stored in capacitors decrease. Due to the above, capacitors with greater capacitance must be considered for shortened lateral gate lengths. Methods for increasing capacitance of a capacitor include increasing capacitor area, and reducing effective thickness of the dielectric layer between plates. In practical applications, reduced memory cell areas and increased capacitor areas cannot be satisfied simultaneously. Reduction of the effective thickness of the dielectric layer is also limited.
Hence, vertical transistor structures are widely applied in the semiconductor industry. By doing so, it is possible to have appropriate gate length for obtaining a low leakage, without reducing the voltage applied on wordlines or increasing the lateral area of memory cells. Moreover, the method also features the formation of a deep trench capacitor directly below the vertical transistor, which greatly reduces the area occupied by memory cells.
A current process for a vertical transistor and a trench capacitor is shown in FIG.
1
. After the formation of a deep trench capacitor C (comprising a plate
20
, a capacitor dielectric layer
18
and a buried plate
16
), a conductive wire (consisting of a collar dielectric layer
21
, a first conductive layer
24
and a second conductive layer
22
) is formed on the capacitor. Next, high density plasma (HDP) is used to form a trench top oxide (TTO)
26
on the conductive wire for isolation. A transistor (consisting of a gate oxide
28
, a conductive layer (not shown), a spacer (not shown), and a source/drain are then formed to complete the vertical transistor and the trench capacitor.
However, in the above-mentioned method, the surface of the TTO
26
, formed by HDP, tends to incline from one end to the other, as shown in FIG.
1
. An ideal TTO with a planar surface is difficult to obtain due to the restrictions of the HDP process. In addition, if uniformity of the TTO is not satisfactory, one sidewall of the trench is not sufficiently protected by the oxide layer, thus insulation is not satisfactory. Consequently, excess ion diffusion (such as As) under the vertical transistor occurs. This brings adverse effects to the reliability of the gate oxide, and overall performance of the element deteriorates.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide a method for forming a vertical transistor and a trench capacitor to overcome conventional problems and meet the quality requirements.
The invention features the formation of the trench top oxide (TTO) by liquid phase deposition (LDP). In a LDP process, a wafer is completely dipped into a chemical solution, thus avoiding the conventional problem of deposition angle associated with the high density plasma process. The trench top oxide is evenly and uniformly formed in the trench to acquire a TTO with a smooth, uniform and planar surface.
In order to achieve the above object, the invention provides a method for forming a vertical transistor and a trench capacitor. The method includes the steps of: providing a semiconductor substrate having a pad stacked layer on the surface and a trench formed therein is provided; forming a trench capacitor at a bottom part of the trench and partially exposes the sidewall; forming a conductive wire on top of the trench capacitor in the trench; forming a dielectric layer on the exposed sidewall of the trench; forming a trench top dielectric by liquid phase deposition on the conductive wire; and
forming a vertical transistor on the trench top dielectric, which isolates the vertical transistor from the trench capacitor.
According to the method provided, a TTO with a planar surface and a uniform thickness is formed. Therefore, an excellent insulation effect is obtained, and reliability of the gate oxide formed in the follow-up steps is enhanced. Semiconductor elements with excellent characteristics are then obtained.
A detailed description is given in the following embodiments with reference to the accompanying drawings.


REFERENCES:
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patent: 5665624 (1997-09-01), Hong
patent: 5831301 (1998-11-01), Horak et al.
patent: 5985729 (1999-11-01), Wu
patent: 6335247 (2002-01-01), Tews et al.
patent: 6368912 (2002-04-01), Chang et al.
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patent: 6552382 (2003-04-01), Wu
patent: 6642566 (2003-11-01), Mandelman et al.

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