Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-07-27
2002-05-21
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S299000, C438S532000
Reexamination Certificate
active
06391751
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor processing technology, and, more particularly, to a method of forming gate electrodes on semiconductor devices.
2. Description of the Related Art
There is a constant drive to reduce the channel length of transistors to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e.g., transistors, formed above the surface of a semiconducting substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnections.
Many modem integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnections must be made in multiple layers to conserve plot space on the semiconducting substrate. This is typically accomplished through the formation of a plurality of conductive lines and conductive plugs formed in alternative layers of dielectric materials formed on the device. The conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. The conductive lines and plugs may be made of a variety of conductive materials, such as copper, aluminum, aluminum alloys, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, etc. These conductive lines and plugs may be formed by a variety of known techniques, e.g., single damascene processing, dual damascene processing, etc.
As feature sizes have continued to decrease, minor variations in the size of various components may adversely impact the performance of the resulting semiconductor device. For example, in forming gate electrodes comprised of polycrystalline silicon (polysilicon), there may be variations or non-uniformity in the shape and configuration of the gate electrode. For example, the sidewalls of the gate electrode may not be as vertical as desired, e.g., there may be an outward flaring toward the bottom of the gate electrode. Additionally, the gate electrode may not be uniform along its width.
FIGS. 1A and 1B
depict illustrative examples of non-uniform gate electrodes. As shown in these figures, the semiconductor device
50
is comprised of a gate dielectric
54
formed above a semiconducting substrate
52
, and a gate electrode
56
, with sidewalls
57
, formed above the gate dielectric
54
.
FIG. 1A
depicts the situation in which there is an undesirable outward flaring of the sidewalls
57
of the gate electrode toward the bottom of the gate electrode
56
.
FIG. 2B
depicts the situation in which the sidewalls
57
of the gate electrode
56
are non-uniform and not as vertical as might be desired.
The non-uniformity of the profile of the gate electrode is due, at least in part, to the grain structure and grain size of the polysilicon gate electrode material, and the etching processes used to form the gate electrode. The problem has become even more problematic as the channel length of modem semiconductor devices becomes smaller and smaller. There are several problems that may arise from such non-uniform gate electrode profiles. For example, in the illustrative situation where the gate electrode is flared outward at the bottom, sidewall spacers that are formed adjacent the gate electrode to insulate the gate electrode from the source/drain regions of the transistor device may be insufficient to adequately insulate the gate electrode from the source/drain regions formed on the device. The flared bottom of the gate electrode also results in the source/drain extension doping implants and halo doping implants being more graded, which is undesirable in advanced CMOS devices. Additionally, if there are variations in the profile of the gate electrode in the width direction, then the electrical field set up when the transistor is turned “on” will vary along the width of the transistor.
The present invention is directed to a method for solving or at least reducing some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of polysilicon, forming a masking layer above the layer of polysilicon, and patterning the masking layer to expose portions of the layer of polysilicon. The method further comprises implanting a dopant material into the exposed portions of the layer of polysilicon to convert the exposed portions of the layer of polysilicon to substantially amorphous silicon, and performing an etching process to remove the substantially amorphous silicon to define a gate electrode.
REFERENCES:
patent: 5545574 (1996-08-01), Chen et al.
patent: 5899732 (1999-05-01), Gardner et al.
patent: 6037204 (2000-03-01), Chang et al.
patent: 6051460 (2000-04-01), Nayak et al.
patent: 6200887 (2001-03-01), Balasubramaniam et al.
patent: 6228766 (2001-05-01), Fujii
Luning Scott D.
Roche William R.
Turnqest Karen L. E.
Wu David Donggang
Advanced Micro Devices , Inc.
Lindsay Jr. Walter L.
Niebling John F.
Williams Morgan & Amerson P.C.
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