Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-07-26
2002-05-21
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S458000, C438S508000, C438S445000
Reexamination Certificate
active
06391799
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a particular process for fabricating a structure comprising a carrier substrate and a layer of semiconductor material on one surface of the carrier substrate.
More particularly, it concerns the forming of a semiconductor-on-insulator structure such as, for example, a structure of silicon carbide-oxide-semiconductor type.
The invention finds applications in the areas of microelectronics and optoelectronics for the fabrication of substrates such as substrates comprising a GaN layer. This material is a semiconductor with a wide forbidden band and allows the fabrication of electro-optic devices such as electroluminescent diodes or lasers which operate in the ultraviolet and blue spectrum.
The invention also finds applications in the manufacture of microsystems able to operate in hostile environments, such as high temperature environments or corrosive atmospheres. In this case, with the process of the invention it is possible, for example, to provide thin membranes of silicon carbide able to withstand the stresses of the hostile environment.
2. Disscussion of the Background
As indicated previously, gallium nitride (GaN) is a material of particular interest on account of its wide forbidden band for the fabrication of electro-optical devices. For such applications, however, it proves to be impossible to obtain monocrystalline GaN blocks of sufficient size.
Therefore, at the present time, substrates are made which comprise one layer of GaN that subjected to heteroepitaxial growth on a sapphire or silicon carbide (SiC) substrate.
The use of sapphire as epitaxial substrate leads to obtaining GaN layers having a high density of crystalline defects. By using silicon carbide (SiC) as epitaxial substrate, it is possible to obtain better crystalline quality—since there is better mesh parameter agreement between GaN and SiC.
The very high cost of monocrystalline SiC substrates is, however, a handicap in its use for epitaxial growth.
On account of the high cost of monocrystalline SiC substrates, it is possible to have recourse to more economical substrates which only comprise a thin superficial layer of SiC on the surface of a basic substrate in silicon.
However, silicon, silicon carbide and the gallium nitride that is subsequently formed have fairly different thermal dilatation coefficients. Considerable stresses and a high defect density therefore occur during the formation of the gallium nitride on this type of substrate.
This problem may be at least partly solved by providing an oxide layer between the silicon and the silicon carbide. This layer brings a reduction in the stresses due to differential dilatation and leads to obtaining a so-called “compliant” substrate.
In known manner, it is for example possible to fabricate structures of silicon carbide-on-insulator type (SiCOI), by forming a layer of SiC through epitaxy on a substrate of silicon-on-insulator type (SOI).
In such cases, however, a thin film of silicon remains from the superficial silicon layer of the SOI, between the SiC and the oxide. This silicon film causes some loss of the “compliant” properties obtained with the oxide layer of the SOI structure. Also, during SiC epitaxy, cavities are formed in the oxide layer and defects occur in the SiC layer.
It is also possible to conduct carburization of the superficial silicon layer of a substrate of silicon-on-insulator (SOI) type, to convert it entirely into SiC and thereby obtain a SiC/Oxide interface with no intermediate silicon.
This solution, however, proves to be difficult to implement insofar as the superficial silicon layer of SOI structures generally has a thickness of a few hundred nanometres. The carburization of silicon only enables a SiC layer to be obtained over a thickness that is in the order of a few dozen nanometres.
Document (1), whose reference is specified at the end of this disclosure, puts forward another process for obtaining a “compliant” substrate comprising a silicon carbide layer on an oxide layer.
According to this document, an oxide layer is formed on the surface of a solid SiC substrate and ions are implanted in the substrate to create a weakened zone therein. This weakened zone delimits in the substrate a superficial layer of SiC in contact with the oxide layer.
The SiC substrate, provided with the oxide layer, is then transferred to a target substrate in silicon by contacting the oxide layer with the target substrate.
Finally heat treatment is applied to cause cleavage of the SiC substrate along the weakened zone and release the superficial SiC layer. This layer remains integral with the target substrate via the insulator layer.
The cleavage of a substrate along a weakened zone using heat treatment is also described in document (2) whose reference is also specified at the end of this disclosure.
The structure finally obtained therefore has, in the following order, a silicon substrate, an oxide layer then a silicon carbide layer.
With the process described above, it is possible to obtain carriers with a SiC layer which are less costly than substrates in monocrystalline SiC. The process does however have a certain number of limitations.
It appears that a relatively high heat schedule (treatment time-treatment temperature) is required for cleavage of the silicon carbide. This heat schedule is for example 1 hour at 850° C. By way of comparison, cleavage of silicon may be brought about with a schedule of only 30 seconds at 500° C.
Also, the cleaved silicon carbide proves to have surface roughness. The SiC surface therefore has to be treated by polishing before other semiconductor materials, such as GaN, can be formed on this surface.
SUMMARY OF THE INVENTION
The purpose of the invention is to put forward a process for fabricating a structure comprising a carrier substrate and a layer of semiconductor material on one surface of this substrate, such as a structure of silicon-on-insulator type, and in particular silicon carbide on insulator, which does not encounter the difficulties or limitations set forth above.
One purpose in particular is to put forward an economical process for fabricating a structure of silicon carbide-oxide-silicon type which does not require a high heat schedule during the cleavage operation.
Another purpose is to propose such a process with which it is possible to obtain a SiC layer having excellent surface condition.
A further purpose is also to put forward a process for fabricating carriers for a GaN layer.
Yet a further purpose is to enable a large-size structure to be obtained (in particular with SiC or GaN layers).
To achieve these purposes, the invention sets out more specifically to propose a process for fabricating a structure comprising a carrier substrate and a layer of semiconductor material on one surface of the carrier substrate, the process comprising the following successive steps:
a) forming a layer of semiconductor material on one surface of a first substrate,
b) implanting ions in the first substrate, underneath said surface, in the vicinity of the layer of semiconductor material, to form a zone, called a cleavage zone, which delimits a superficial layer in the first substrate, in contact with the layer of semiconductor material,
c) transferring the first substrate, with the layer of semiconductor material, onto the carrier substrate, the layer of semiconductor material being made integral with the carrier substrate,
d) providing energy to cause cleavage of the first substrate along the cleavage zone, the superficial layer of the first substrate remaining integral with the layer of semiconductor material and with the carrier substrate during cleavage,
e) removing said superficial layer to uncover the layer of semiconductor material.
According to one advantageous embodiment, the supply of energy for step d) is chosen from among a supply of thermal energy, mechanical energy, or a combination of these energies.
By supply of thermal energy is meant the application of heat treatment.
This heat treatment may be applied using a heat schedul
Commissariat a l′Energie Atomique
Everhart Caridad
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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