Method for forming vertical polysilicon diode compatible with CM

Details Method for forming vertical polysilicon diode compatible with CM Method for forming vertical polysilicon diode compatible with CM

1997-02-20

1998-02-10

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438237, 438328, 438173, 438335, 148DIG139, 148140, 257653, 257654, H01L 218238

Patent

active

057168806

ABSTRACT:
A method for forming a diode for use within an integrated circuit, and a diode formed through the method. There is first provided a semiconductor substrate. There is then formed over the semiconductor substrate a dielectric layer. There is then formed upon the dielectric layer a first polysilicon layer, where the first polysilicon layer has a first dopant polarity and a first dopant concentration. There is then formed at least in part overlapping and at least in part in contact with the first polysilicon layer a second polysilicon layer. The second polysilicon layer has a second dopant polarity and a second dopant concentration, where the second dopant polarity is opposite to the first dopant polarity. A first portion of the second polysilicon layer overlapping and in contact within a first portion of the first polysilicon layer forms a junction diode. The method and the diode formed through the method are compatible with complementary metal oxide semiconductor (CMOS) integrated circuit fabrication methods and bipolar complementary metal oxide semiconductor (BiCMOS) integrated circuit fabrication methods.

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patent: 5466622 (1995-11-01), Cappelleti
patent: 5471087 (1995-11-01), Buerger, Jr.
patent: 5478764 (1995-12-01), Inoue

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