Method for forming vertical channel transistor of...

Details Method for forming vertical channel transistor of... Method for forming vertical channel transistor of...

2008-12-12

2010-12-14

Sarkar, Asok K (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21410, C257SE21629, C257SE21643, C257SE21693, C438S209000, C438S212000

Reexamination Certificate

active

07851293

ABSTRACT:
A method for forming a vertical channel transistor in a semiconductor device includes providing a substrate, forming pillar patterns extending perpendicular from the upper surface of the substrate, forming a spin on carbon (SOC) layer in a gap region between the pillar patterns, forming photoresist patterns above a resultant structure where the SOC layer is filled to expose a region for an isolation trench, etching the SOC layer between the photoresist pattern barriers to expose the region for the isolation trench, and etching the exposed structure to a certain depth forming the isolation trench.

REFERENCES:
patent: 7247570 (2007-07-01), Thomas
patent: 7271413 (2007-09-01), Chance et al.
patent: 7631874 (2009-12-01), Webb
patent: 7663183 (2010-02-01), Brar et al.
patent: 2007/0190766 (2007-08-01), Seo et al.
patent: 1019990088580 (1999-12-01), None
patent: 100506336 (2005-07-01), None
Korean Notice of Allowance for Korean Patent Application No. 10-2008-0047084.

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