Method for forming vertical channel flash memory cell using P/N

Details Method for forming vertical channel flash memory cell using P/N Method for forming vertical channel flash memory cell using P/N

1997-12-22

2000-10-03

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438270, 438589, H01L 218247

Patent

active

061272264

ABSTRACT:
This is a method of forming a vertical memory device on a semiconductor substrate. Start by forming an initial mask with a first array of parallel strips, with a first orientation, on the surface of a silicon oxide layer on a substrate. Then form another mask with transverse strips to form gate trench openings between the first array of strips and the transverse strips. Next, etch floating gate trenches in the substrate through the gate trench openings. Dope the walls of the trenches with a threshold implant and remove exposed portions of the mask. Form source/drain regions in the substrate self-aligned with the floating gate electrode. Strip the remainder of the masks. Form a tunnel oxide layer on the trench surfaces and a floating gate electrode in the trench on the tunnel oxide layer. Above the source/drain regions, form source drain conductor lines in the substrate in a parallel array. Form an ONO dielectric layer and a control gate electrode over the top surface of the floating gate electrode and an array of P/N isolation regions in the silicon semiconductor substrate.

REFERENCES:
patent: 5045490 (1991-09-01), Esquivel et al.
patent: 5229312 (1993-07-01), Mukherjee et al.
patent: 5429970 (1995-07-01), Hong
patent: 5468663 (1995-11-01), Bertin et al.
patent: 5563083 (1996-10-01), Pein
patent: 5587949 (1996-12-01), Bergemont et al.
patent: 5595927 (1997-01-01), Chen et al.

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