Method for forming ultra-shallow junction of semiconductor devic

Details Method for forming ultra-shallow junction of semiconductor devic Method for forming ultra-shallow junction of semiconductor devic

1997-09-15

1998-06-30

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438297, 438301, 438308, 438369, 438378, 438530, 438540, 438550, 257344, H01L 218238

Patent

active

057733376

ABSTRACT:
There is disclosed a method for forming an ultra-shallow junction of a semiconductor device, comprising a four-stage RTA process following the ion implantation of dopants for source/drain junction, the RTA process being carried out with high temperature-elevating and -quenching rates between the stages, in such a way that relatively low temperatures are used for a short time in the first three stages in order to eliminate only the point defects, which greatly affect the diffusion of dopants, without diffusion of dopants while a relatively high temperature is taken in the last stage with the aim of allowing the dopants to diffuse a little to p.sup.+ and n.sup.+ shallow junctions, thereby obtaining an improvement in electrical activity and reducing junction current leakage and thus, improving the properties and reliability of the resulting semiconductor device.

REFERENCES:
patent: 4042419 (1977-08-01), Heinke et al.
patent: 5399506 (1995-03-01), Tsukamoto
patent: 5411906 (1995-05-01), Johnson et al.
patent: 5552332 (1996-09-01), Tseng et al.
patent: 5605854 (1997-02-01), Yoo
patent: 5668024 (1997-09-01), Tsai et al.

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