Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-17
2002-05-21
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S228000, C438S229000, C438S232000, C438S514000, C257S371000
Reexamination Certificate
active
06391700
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method for forming semiconductor devices process, and more particularly to a method for forming a twin-well of the semiconductor devices.
2. Description of the Prior Art
The escalating requirements for high densification and performance associated with ultra large scale integration (ULSI) semiconductor devices requires minimal design features, and under, increased transistor and circuit speeds, high reliability and increase manufacturing throughput for competitiveness. The reduction of design features to 0.25 micron and under generates acute problems challenging the limitations of conventional semiconductor manufacturing technology, particularly for increased manufacturing throughput and cost reduction. There are rugged topographies during fabricating a semiconductor device structure, and these rugged topographies can be used as alignment marks of the lithography steps. For example, the field oxide isolation layer is formed on the silicon substrate that can be used as alignment marks of the lithography steps for following polysilicon gate process.
As integrated circuits are miniaturized more and more, these devices introduce a vertical structure more often than a conventional planar structure. Various problems are encountered in the manufacture, for example, with a twin-well process of an integrated circuit device. One problem is that the topography between N-well and P-well of a twin-well device is not at the same horizontal level that lowers the production line throughout. Therefore, it will need an extra photo-mask for zero layer alignment to avoid this phenomenon. The circuit layout patterns are transferred from photo-masks to the surface of the silicon wafer using a photolithography process. Each layer followings the zero layer must be carefully aligned to the previous pattern on the wafer. Alignment marks are introduced on each mask and transferred to the wafer as part of the integrated circuit pattern. This process will increase the number of manufacturing steps and the production cost.
As illustrated in
FIG. 1A
to
1
D, continuously forming a pad oxide layer
110
and a nitride layer
120
on a substrate
100
. The photo-resist layer
130
is selectively patterned on the nitride layer
120
by a conventional lithography method. The nitride layer
120
is partially etched by using etch method with the photo-resist pattern
130
as a mask to define an N-well region
150
. The N-type ion-implant
140
is performed by the photo-resist pattern
130
as a mask to form an N-doped region
150
in the substrate
100
. Then, the photo-resist pattern
130
is removed. The well-oxide layer
160
is grown over the N-well region
150
. Next, the nitride layer
120
is stripped by etch method. The P-type ion-implant
170
is performed by means of the well-oxide layer
160
as a mask to form the P-doped regions
180
in the substrate
100
. Performing the well drive-in step form the twin-well in the substrate
100
. Finally, the well-oxide layer
160
and pad oxide layer
110
are removed to finish the twin-well process. This twin-well process has a difference
190
in level between the surface of the N-well and P-well.
As illustrated in
FIG. 2A
to
2
F, continuously forming a pad oxide layer
205
A and a nitride layer on a substrate
200
. The photo-resist layer is formed on the nitride layer, and patterned selectively by the lithography method to form a photo-resist mask
215
A and alignment mark photo-resist patterns
215
B. The nitride layer is partially etched by using etch method with the photo-resist mask
215
A and an alignment mark photo-resist pattern
215
B as the etching masks to form an nitride layer
210
A and alignment marks
210
B. Then, the photo-resist mask
215
A and an alignment mark photo-resist pattern
215
B are removed. The N-well photo-resist
220
is formed on the nitride layer
210
A, then performing an N-type ion-implant
225
through the nitride layer
210
A and the pad oxide layer
205
A into the substrate
200
by means of the N-well photo-resist
220
as a mask to form an N-doped region
230
. Then, the N-well photo-resist
220
is removed. The P-well photo-resist
235
is formed on the nitride layer
210
, then performing a P-type ion-implant
240
through the nitride layer
210
and the pad oxide layer
205
A into the substrate
200
by means of the P-well photo-resist
235
as a mask to form a P-doped region
245
. Then remove the P-well photo-resist
235
and proceed with the drive-in process to form the N-well
250
and P-well
255
. The actively region photo-resist layers
260
are defined selectively on the nitride layer
210
of the N-well
250
and P-well
255
segments. Next, the nitride layer
210
A is etched by the actively region photo-resist layers
260
as the etching masks to form the nitride layers
210
C. Thereafter, the actively region photo-resist layers
260
are stripped. The part of the pad oxide
205
A between the nitride layers
210
C is grown to form a field oxide (FOX)
205
B. Finally, all of the nitride layers
210
C and the pad oxide
205
A are stripped but remained field oxide (FOX)
205
B.
As illustrated in
FIG.3A
to
3
E, forming a pad oxide layer
305
on a substrate
300
. A zero photo-resist layer
310
is selectively patterned by a zero lithography method to define the zero trenches. The pad oxide layer
305
is partially etched by using etch method with the photo-resist pattern
310
as a mask to form the zero trenches
315
, wherein the zero trenches
315
are the alignment marks for the follow-up process. The N-well photo-resist layer
320
is selectively patterned by a conventional lithography method. The N-type ion-implant
325
is performed by the N-well photo-resist pattern
320
as a mask to form an N-doped region
330
in the substrate
300
. After the well-oxide layer
335
is grown over the N-doped region
330
, removing the N-well photo-resist pattern
320
. The P-type ion-implant
340
is performed by means of the well-oxide layer
335
as a mask to form a P-doped region
345
in the substrate
300
. The pad oxide
305
and the well-oxide layer
335
are then removed. Finally, performing the well drive-in step form the twin-well in the substrate
300
, but there is a difference
360
in level between the surface of the N-well
350
and P-well
355
.
These twin-well processes of above are not only complicated but also to form rugged topographies on the substrate, as shown in FIG.
1
D and FIG.
3
E. The difference in level will result in the production cost increasing, and the rugged topographies affect the succeeding lithography process yet, so that the critical dimension is more difficult to control during the sub-micron process. Although the alignment marks had made for follow-up lithography process, as shown in FIG.
2
A and
FIG. 3A
,
3
B, the alignment between the N-well and the P-well can be not checked whether it is exact. Furthermore, these twin-well processes of above are complicated due to add the zero layer process.
In accordance with the above description, a new and improved method for forming the twin-well regions of semiconductor devices is therefore necessary, so as to raise the yield and quality of the follow-up process.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for fabricating twin-well regions of the semiconductor devices that substantially overcomes drawbacks of above mentioned problems arised from the conventional methods.
Accordingly, it is a main object of the present invention to provide a method for fabricating the twin-well regions of semiconductor devices, so as to form surface without rugged topographies to solve the issues of the succeeding lithography process. Hence, the method of the present invention is appropriate for deep sub-micron technology to provide the semiconductor devices.
Another object of the present invention is to provide a method for forming the twin-well regions. The present invention can simplify manufacturi
Blum David S
Bowers Charles
Frazer & Murphy
Goldstein Powell
United Microelectronics Corp.
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