Method for forming twin gate CMOS

Details Method for forming twin gate CMOS Method for forming twin gate CMOS

1999-06-25

2001-07-10

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S782000, C427S240000

Reexamination Certificate

active

06258643

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a twin gate CMOS, wherein small dimension and more quality fabrication can 10 be achieved.
2. Description of the Prior Art
In the conventional method for manufacturing twin gate transistors, the gates of the transistor are first defined on an undoped conducting layer, generally, followed by a channel implantation, which forms the source/drain terminals such that the conducting layer of the gate is doped in situ to increase its electrical conductivity. With the current trend of heavy reduction of semiconductor component dimensions in integrated circuits and the importance of preventing the short channel effect in the transistors due to excessive thickness in the source/drain diffusion regions, such layers have had to become thinner and thinner; and as a result, the impurity concentration resulting from channel implantation is also necessarily becoming lighter and lighter. Therefore, after the ion doping operation the impurity concentration in the conducting layer of the gate may be insufficient, which leads to an increase in sheet resistance and may affect both its electrical conductivity and the threshold voltage (Vt) level of the transistor.
In an improved version of the conventional method of fabricating a twin gate CMOS, in order to lessen the effects on threshold voltage level caused by low impurity concentration in the gates of the twin gate transistor, a heavier doping of impurities is performed in situ with the formation of the conducting layer of the transistor. The details of such a method are illustrated in
FIGS. 1A through 1G
.
First, referring to
FIG. 1A
, a P-well
140
and a N-well
160
, with an isolating region
180
there between, are formed adjacent to each other on a P-type silicon substrate
100
. Then the isolating region
180
is formed of an insulating material such as silicon dioxide. Next, a thermal oxidation method is used to form a gate oxide layer
200
on the substrate surface, and thereafter, chemical vapor deposition (CVD) is used to form a conductive layer
210
above the gate oxide layer
200
. The conductive layer
210
, for example, can be a polysilicon layer formed by deposition using disilane gas (Si
2
H
6
) and with P-type ion doping, for example, using diborane (B
2
H
6
), performed in situ for convening the polysilicon layer into a P
+
-type polysilicon layer
210
. Then, a first photoresist layer
230
is formed over the surface of the P
+
-type polysilicon layer
210
above the N-type well
160
.
Referring to
FIG. 1B
, in a subsequent step the exposed P
+
-type polysilicon layer
210
is etched until the upper surface of the gate oxide layer
200
is exposed. Then, the first photoresist layer
230
is removed. The CVD is again used to form a polysilicon layer
250
on the surfaces of the exposed gate oxide layer
200
and P
+
-type polysilicon layer
210
. The deposition uses disilane gas with N-type ion doping, for example, PH
3
performed in situ doped, to convert the polysilicon layer into an N
+
-type polysilicon layer
250
.
Referring next to
FIG. 1C
, in the subsequent step a second photoresist layer
270
is formed over the surface of the N
+
-type polysilicon layer
250
above the P-type well region
140
, and then is etched back until the upper surface of the P
+
-type polysilicon layer
210
is exposed.
Referring next to
FIG. 1D
, the second photoresist layer
270
is removed. Then, using a conventional photolithographic technique, a third photoresist layer
290
is formed above the respective N
+
-type
250
and P
+
-type polysilicon layer
210
as a mask for defining the gates in subsequent steps. Due to misalignment of photoresist layer
270
, there may be a gap in between the N
+
-type
250
and P
+
-type polysilicon layer
210
in the following etch step.
Referring next to
FIG. 1E
, with the third photoresist layer as a mask, the P
+
and N
+
type polysilicon layers are etched to mark out a P
+
-type polysilicon gate
330
and an N
+
-type polysilicon gate
310
, and then the third photoresist layer is removed. Sequentially, under high heat and in a steamy environment, thin layer of oxide
500
P and
500
N are formed on the respective surfaces of the P
+
-type
330
and N
+
-type polysilicon gate
310
. Next, a conventional photolithographic technique is again used to form a fourth photoresist layer
370
over the surface of the gate oxide layer SOOP above the N-type well regions
160
and covering up the P
+
-type polysilicon gate
330
. Subsequently, N-type ions, for example, arsenic ions
390
I, is used in a channel implantation process, to form N
+
-type source/drain of diffusion regions
390
on the substrate surface, on each side of the N
+
-type polysilicon gate
310
, thus completing the NMOS part of the CMOS component.
Referring next to
FIG. 1F
, in the subsequent step a fifth photoresist layer
410
is formed over the surface of the thin oxide layer
500
N above the P-type well
140
and covering up the N
+
-type polysilicon gate terminal
310
. Subsequently, P-type ions, for example, boron fluoride ions
430
I, is used in a channel implantation process, to forming P
+
-type source/drain of diffusion regions
430
on the substrate surface on each side of the P
+
-type polysilicon gate
330
, thus completing the PMOS part of the CMOS component. Next, referring to
FIG. 1G
, the fifth photoresist layer
410
is removed to complete the twin gate transistor.
Although the improved method for fabricating conventional twin-gate CMOS mentioned previously can solve the problem of unstable threshold voltage causes by low doping density for twin-gate, there still comes with the following disadvantages. For in-situ doped P
+
-type gates, due to the high doping concentration at the interface between a P
+
-type polysilicon layer and a gate oxide layer, boron ions might easily penetrate through the gate oxide layer, hence, results in a shifting of the threshold voltage. Moreover, referring to what is shown in
FIG. 1C
, when taking photoresist
270
as a mask to etch N
+
-type polysilicon layer, it is easy to result in a disconnection between P
+
-type and N
+
-type polysilicon layer, like what is shown in
FIG. 1D
, due to the mis-alignment of photoresist
270
. Thus, this disconnection will result in an entire circuit malfunction in CMOS circuits wherein P
+
-type and N
+
-type polysilicon layer connections are usually needed.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for fabricating twin gate CMOS. Owing to the use of a method, so that the provided twin gate CMOS can be adapted small dimension and more quality fabrication.
Another purpose of the present invention is to provide a twin gate CMOS with an amorphous silicon layer, thereby avoiding boron and boron fluoride to penetrate through gate oxide into N-well region.
A further purpose of the present invention is to provide for fabricating twin gate CMOS. Thereby misalignment problem in the photoresist layer which results in a disconnection between P
+
-type and N
+
-type polysilicon layer can be solved.
In one embodiment, the present invention provides a twin gate CMOS, which includes isolations formed in a semiconductor substrate. A P-well and N-well are formed on two sides of the isolation. Next, then a gate oxide layer is formed on the P-well and N-well. An N
+
-type polysilicon layer in-situ doped with N-type ions is formed on the gate oxide layer. Sequentially, a cap oxide layer is deposited and a first photoresist layer is formed in order on the N
+
-type polysilicon layer, wherein etching respective patterns on the cap oxide layer and the N
+
type polysilicon layer until the gate oxide is exposed. Then, form an amorphous silicon layer above the surfaces of the exposed gate oxide layer and the cap oxide layer, then doped with P-type

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