Method for forming twin bit cell flash memory

Details Method for forming twin bit cell flash memory Method for forming twin bit cell flash memory

2003-11-19

2004-10-26

Chen, Jack (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S288000, C438S261000, C438S266000

Reexamination Certificate

active

06808991

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for manufacturig a flash memory device, and more particularly to a method of fabricating a nitride read only memory with dual oxide-nitride-oxide (ONO) gate segments and two bits per cells.
BACKGROUND OF THE INVENTION
Flash memory devices are used extensively for computer external storage. One of the goals in manufacturing flash memory is to store a maximum amount of information using a minimum amount of semiconductor surface area. Another goal of flash memory fabrication is use of a simple, inexpensive, yet high yield process. Many previous methods for reducing device size add too much complexity and cost. One relatively recent technique stores two bits in one cell for the purpose for reducing device size. Nitride read only memory (also called N-bit) cells can be used to accomplish this technique.
FIG. 1
illustrates an example prior art Nitride dual bit cell. As illustrated, two separately chargeable areas
100
and
101
are found within a nitride layer
102
formed in an oxide
103
-nitride-oxide
104
(ONO) sandwich underneath a polysilicon layer
105
. However, some leakage occurs between the first and second bit areas through the Nitride
102
. When the first bit area
100
is charged, electrons leak through nitride
102
to second bit area
101
. The threshold voltage in second bit area
101
can be influenced by the leaked charge, and the data stored in the second bit could be lost. This problem in dual bit cells is sometimes known as the second bit effect.
In view of the drawbacks of the prior method, it is necessary to provide a method that can reduce the cost and complexity in flash memory fabrication and prevent the problem of second bit effect of N-bit memory.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a method of fabricating flash memory cells with twin bit cells, and reduce the problem of the second bit effect.
It is another object of this invention to reduce the cost and complexity in a fabrication process by self-aligning the buried diffusion implant region and the ONO segment in one process.
Roughly described, therefore, in accordance with a preferred embodiment of the present invention, a method is provided for fabricating an N-bit memory device with self-aligned buried diffusion implants and two isolated ONO segments in one cell. The method includes the steps of forming an ONO layer on a substrate, depositing a polysilicon layer, patterning the polysilicon layer, implanting barrier diffusion, trimming the photoresist layer on the polysilicon layer, etching the polysilicon layer by using the trimmed photoresist layer as mask, then removing the photoresist. After removing the photoresist, a nitride layer is filled in the patterned polysilicon layer openings. The etching steps are preformed by using the nitride layer as a mask. The polysilicon layer and part of the ONO layer are removed, and the gate oxide layer is exposed. Two isolated ONO segments are formed by these etching steps. A polysilicon gate is then formed on the gate oxide layer.
The embodiment uses photoresist trimming and a polysilicon hardmask method to self-align buried diffusion implant regions and to slice ONO segments. Hence, two ONO segments can be read and be programmed independently to form a twin bit cell structure. The problem of second bit effect of N-bit in the prior art thus can be reduced.


REFERENCES:
patent: 6011725 (2000-01-01), Eitan
patent: 6051470 (2000-04-01), An et al.
patent: 6376308 (2002-04-01), Wang et al.
patent: 6461949 (2002-10-01), Chang et al.
patent: 6518103 (2003-02-01), Lai
patent: 6538292 (2003-03-01), Chang et al.
patent: 2003/0040152 (2003-02-01), Liu et al.

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