Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-11-20
2003-11-11
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C148SDIG001
Reexamination Certificate
active
06645815
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to trench MOSFET devices, and more particularly to trench MOSFET devices having low parasitic resistance.
A trench MOSFET (metal-oxide-semiconductor field-effect transistor) is a transistor in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin insulator layer such as an oxide layer and filled with a conductor such as polysilicon (i.e., polycrystalline silicon), allows less constricted current flow and thereby provides lower values of specific on-resistance. Examples of trench MOSFET transistors are disclosed, for example, in U.S. Pat. Nos. 5,072,266, 5,541,425, 5,866,931 and 6,031,265, the disclosures of which are hereby incorporated by reference.
As a specific example,
FIG. 1
illustrates half of a hexagonally shaped trench MOSFET structure
21
disclosed in U.S. Pat. No. 5,072,266. The structure includes an n+ substrate
23
, upon which is grown a lightly doped n epitaxial layer
25
of a predetermined depth d
epi
. Within the epitaxial layer
25
, p body region
27
(p, p+) is provided. In the design shown, the p body region
27
is substantially planar (except in a central region) and typically lays a distance d
min
below the top surface of the epitaxial layer. Another layer
28
(n+) overlying most of the p body region
27
serves as source for the device. A series of hexagonally shaped trenches
29
are provided in the epitaxial layer, opening toward the top and having a predetermined depth d
tr
. The trenches
29
are typically lined with oxide and filled with conductive polysilicon, forming the gate for the MOSFET device. The trenches
29
define cell regions
31
that are also hexagonally shaped in horizontal cross-section. Within the cell region
31
, the p body region
27
rises to the top surface of the epitaxial layer and forms an exposed pattern
33
in a horizontal cross section at the top surface of the cell region
31
. In the specific design illustrated, the p+ central portion of the p body region
27
extends to a depth d
max
below the surface of the epitaxial layer that is greater than the trench depth d
tr
for the transistor cell so that breakdown voltage is away from the trench surface and into the bulk of the semiconductor material.
A typical MOSFET device includes numerous individual MOSFET cells that are fabricated in parallel within a single chip (i.e., a section of a semiconductor wafer). Hence, the chip shown in
FIG. 1
contains numerous hexagonal-shaped cells
31
(portions of five of these cells are illustrated). Cell configurations other than hexagonal configurations are commonly used, including square-shaped configurations. In a design like that shown in
FIG. 1
, the substrate region
23
acts as a common drain contact for all of the individual MOSFET cells
31
. Although not illustrated, all the sources for the MOSFET cells
31
are typically shorted together via a metal source contact that is disposed on top of the n+ source regions
28
. An insulating region, such as borophosphosilicate glass (not shown) is typically placed between the polysilicon in the trenches
29
and the metal source contact to prevent the gate regions from being shorted with the source regions. Consequently, to make gate contact, the polysilicon within the trenches
29
is typically extended into a termination region beyond the MOSFET cells
31
, where a metal gate contact is provided on the polysilicon. Since the polysilicon gate regions are interconnected with one another via the trenches, this arrangement provides a single gate contact for all the gate regions of the device. As a result of this scheme, even though the chip contains a matrix of individual transistor cells
31
, these cells
31
behave as a single large transistor.
It has been found that, as the sheet resistance over the p-body increases, the voltage drop across the p-body also increases, making the parasitic NPN transistor formed by the source, body and drain more susceptible to being incidentally turned on. For example, during avalanche breakdown, the parasitic transistor can be activated incidentally, which can seriously degrade the overall performance of the device and can even cause permanent damage to the device.
One approach by which the resistance of the body region (and hence the voltage drop across the body region) can be decreased in a trench MOSFET device is described in U.S. Pat. No. 6,031,265.
FIG. 2
is taken from this patent and illustrates a portion of a trench MOSFET in which an N+ substrate
105
supports an N epi-layer
110
. Each transistor cell of this device includes a trenched gate
125
, an N+ source region
140
, and a P-body region
130
. An insulation layer
145
is also provided as is typical. Each transistor cell further includes a deep P+ region
138
formed in the P-body region. The deep P+ region
138
has a higher P-dopant concentration than the surrounding P-body, lowering the parasitic resistance of the P-body region
130
and improving the robustness of the transistor cell. This is achieved because the voltage drop across the body regions of the device is reduced, likewise reducing the parasitic resistance and hence reducing the likelihood of incidentally turning on the parasitic NPN transistors. A shallow P+ region
139
is further provided in the body region
130
to reduce the contact resistance at the metal contact
170
.
In the process described in U.S. Pat. No. 6,031,265, the P-type dopant used to form deep P+ regions
138
and shallow P+ regions
139
is implanted through final contact apertures formed in the insulating layer
145
. Because the dopant can move into the channel of the body region
130
(which is found along the trenched gate
125
) during subsequent diffusion and adversely impact device performance, care should be taken to ensure that the P-dopant is implanted sufficiently far from the channel. However, this action can restrict the use of wider insulating layer
145
apertures, because such use would place the P-dopant near the channel. Wider insulating layer
145
apertures may be desired, for example, because they provide greater contact area for the source regions
140
of the device.
SUMMARY OF THE INVENTION
The present invention provides an improved method for forming trench MOSFET devices with low parasitic resistance.
According to an embodiment of the invention, a method is provided for forming a device that comprises a plurality of trench MOSFET cells. The method comprises: (a) providing a substrate of a first conductivity type; (b) depositing an epitaxial layer of first conductivity type over the substrate, where the epitaxial layer has a lower majority carrier concentration than the substrate; (c) etching trenches into the epitaxial region from an upper surface of the epitaxial layer; (d) forming a first insulating region which lines at least a portion of the trenches; (e) forming a conductive region within the trenches and adjacent the first insulating region; (f) forming body regions of a second conductivity type within an upper portion of the epitaxial layer; (g) forming source regions of the first conductivity type within upper portions of the body regions adjacent the trenches; (h) forming an patterned implantation mask comprising a patterned second insulating region over the epitaxial layer, wherein the patterned implantation mask has apertures over at least portions of the body regions adjacent the sources, wherein the patterned implantation mask covers at least portions of the conductive region, and wherein the patterned implantation mask covers at least portions of the source regions; (i) forming shallow dopant regions by a process comprising: (1) implanting a first dopant of the second conductivity type at a first energy level within upper portions of the body regions through the apertures and (2) diffusing the first dopant at elevated temperatures to a first depth from the upper surface of the epita
Amato John E.
Hshieh Fwu-Iuan
Pratt Brian D.
So Koon Chong
Bonham, Esq. David B.
Fourson George
General Semiconductor Inc.
Mayer Fortkort & Williams PC
Pham Thanh V
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