Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-02-01
2005-02-01
Blum, David S. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S230000, C438S303000, C438S514000
Reexamination Certificate
active
06849489
ABSTRACT:
A gate electrode is formed over but is insulated from a semiconductor body region for each of first and second transistors. Off-set spacers are formed along side-walls of the gate electrode of each of the first and second transistors. After forming the off-set spacers, a DDD implant is performed to form DDD source and DDD drain regions in the body region for the first transistor. After the DDD implant, main spacers are formed adjacent the off-set spacers of at least the first transistor. A LDD implant is performed to form LDD source and LDD drain regions for the second transistor. After forming the main spacers, a source/drain (S/D) implant is carried out to form a highly doped region within each of the DDD drain and DDD source regions and each of the LDD drain and LDD source regions.
REFERENCES:
patent: 4939558 (1990-07-01), Smayling et al.
patent: 5716861 (1998-02-01), Moslehi
patent: 5780891 (1998-07-01), Kauffman et al.
patent: 5793089 (1998-08-01), Fulford, Jr. et al.
patent: 5918125 (1999-06-01), Guo et al.
patent: 5920783 (1999-07-01), Tseng et al.
patent: 6143606 (2000-11-01), Wang et al.
patent: 6187619 (2001-02-01), Wu
patent: 6330187 (2001-12-01), Choi et al.
patent: 6346725 (2002-02-01), Ma et al.
patent: 6350665 (2002-02-01), Jin et al.
patent: 6512273 (2003-01-01), Krivokapic et al.
Chou Kai-Cheng
Rabkin Peter
Wang Hsingya Arthur
Blum David S.
Hynix / Semiconductor Inc.
Townsend and Townsend / and Crew LLP
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