Method for forming three dimensional semiconductor structure...

Details Method for forming three dimensional semiconductor structure... Method for forming three dimensional semiconductor structure...

2001-12-11

2003-05-06

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000

Reexamination Certificate

active

06559004

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the method for forming three dimensional structure, such as three dimensional MINCAP (minimized capacitor) structure, and also relates to the method for forming the three dimensional capacitor.
2. Description of the Prior Art
Structures of some contemporary semiconductor devices are more complex than the combination of multilevel interconnections and elements, such as transistor, in and on the substrate. As usual, these semiconductor devices have at least one element that is disposed over substrate and directly contacted with interconnections. For example, the MINCAP has a capacitor whose plates are contacted with a metal structure, such as metal lines, and an overlying metal structure separately.
One popular conventional structure of these semiconductor devices is shown in FIG.
1
A. As
FIG. 1A
shows, first dielectric layer
11
is disposed on substrate
10
, metal structure
12
, which is one level of the multilevel interconnections, is disposed at the top of the surface of first dielectric layer
11
, and second dielectric layer
13
is disposed on first dielectric layer
11
. Bottom plate
14
, third dielectric layer
15
, and top plate
16
forms the capacitor which is disposed over first dielectric layer
11
and within second dielectric layer
13
. Second metal structures
17
, which are another level of the multilevel interconnections, are essentially disposed over second dielectric layer
13
. Moreover, second metal structures
17
also pierce through second dielectric layer
13
and are contacted with both first metal structure
12
and bottom plate
14
. In addition, possible cap layer(s), possible etch stop layer(s), and possible liner(s) are all omitted to simplify FIG.
1
A.
Clearly, this structure is easy to be formed for each part could be formed by conventional lithography and etch process. However, this structure can not avoid following disadvantage: First, because bottom plate
14
must be insulated from top plate
16
, three masks are require to form bottom plate
14
, third dielectric layer
15
, and top plate
16
separately. Second, large topography leads to difficulty in sequent lithography process(es) and etch process(es). Third, owing to area of both plates
14
/
16
is increased to increase capacitance of capacitor, occupied area of capacitor is large and then available packaged density of this structure is limited.
Another popular conventional structure of these semiconductor devices is shown in FIG.
1
B. As
FIG. 1B
shows, first dielectric layer
11
is disposed over substrate
10
and first metal structure
12
is disposed at the top of the surface of first dielectric layer
11
. Third dielectric layer
15
and top plate
16
are disposed over first metal structure
12
in sequence while first metal structure
12
playing the role of bottom plate
14
. Second metal structure
17
which are another level of the multilevel interconnections, are essentially disposed over second dielectric layer
13
. Moreover, second metal structures
17
also pierce through second dielectric layer
13
and are contacted with both first metal structure
12
and top plate
16
. In addition, possible cap layer(s), possible etch stop layer(s), and possible liner(s) are all omitted to simplify FIG.
1
B.
Clearly, this structure can reduced required mask for top plate
16
and third dielectric layer
15
being formed by the same mask and no mask being required to form non-existent bottom plate
14
. However, this structure can not avoid following disadvantages: First, even capacitor and first metal structure
12
is overlapped, occupied area still is limited by the tendency of increasing plate area to increase capacitance. Second, topography causes problem on coating process if spin-on low-k dielectric material. Third, top plate
16
is difficult to be patterned for weak alignment signal resulted from highly reflective top plate metal and smooth post planarized surface. Fourth, reliability concerns due to possible roughness of first metal structure
12
.
Accordingly, current fabrications of popular structures of all contemporary semiconductor devices which have capacitor within multilevel interconnections are not prefect. Thus, further improvement is required to let fabrication of these devices, such as MINCAP, be more effective, more large alignment tolerance, more easy to be product, and more easy to be with damascene process.
SUMMARY OF THE INVENTION
According to previous defects of conventional technology, one main object of this invention is to provide a method for forming the three dimensional semiconductor structure which replaces horizontal plates of capacitor by vertical plates.
Further, another main object of this invention is to provide methods for forming two possible structures of capacitor.
This invention provides a method for forming a three dimensional semiconductor structure which has vertical capacitor(s) but not horizontal capacitor(s). The method essentially at least includes these steps of forming bottom plates within dielectric layers, forming another dielectric layer over bottom plates, removing all dielectric layers over bottom plates, forming optional liner(s) and capacitor dielectric layers on bottom plates, and forming top plates over capacitor dielectric layers. Note that shape of bottom plates is alike to the bottom connection and verticle fingers, also note that each gap within bottom plates is filled by both capacitor dielectric layer and top plate.
The invention also provides methods for forming two possible capacitor structures. One present method is a method for forming a three dimensional capacitor, essentially at least includes following steps: forming an undulatory bottom plate, forming a dielectric layer on the undulatory bottom plate, and forming an undulatory top plate on the dielectric layer. Another present method is a method for forming a capacitor, at least includes these steps of forming numerous first plates, where first plates are arranged in a sequence and each first plate is separated from others so let numerous gaps be formed, where each gap is disposed between two adjacent first plates; forming numerous second plates so let each said second plate be disposed in one gap, where each second plate is separated from other second plates and first gaps; and forming a dielectric layer within gaps so let each gap be essentially filled by dielectric layer and one second plate.


REFERENCES:
patent: 6331471 (2001-12-01), Lee et al.

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