Method for forming steep spacer in a MOS device

Details Method for forming steep spacer in a MOS device Method for forming steep spacer in a MOS device

2001-01-19

2003-02-11

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06518137

ABSTRACT:

BACKGROUND OF THE INVENTIONS
1. Field of the Invention
The present invention generally relates to a method for forming a spacer in a MOS (metal-oxide-semiconductor) device, and more particularly to a method for fabricating steep spacers in a MOS device.
2. Description of the Prior Art
Spacers play an important role in hot carrier immunity of the MOS device. Spacers in a MOS device are formed by anisotropically etching a conformal dielectric layer, such as TEOS (tetra-ethyl-ortho-silicate) or silicon nitride.
FIG. 1
shows a standard, conventional MOS device, or MOS transistor. A substrate
100
with source/drain
110
formed therein is provided. Field isolation region
120
, such as FOX (Field Oxidation), is formed on the substrate such that active area is among field isolation region
120
. A gate electrode structure, including a gate dielectric layer
122
and a poly gate layer
124
, is formed on the substrate
100
. Spacer
130
is then formed on the sidewall of the gate electrode structure. Source/drain region
110
is then formed by ion-implantation.
In general, the shape of spacer is not steep enough. The oblique spacer
130
is easy to bridge the source/drain region
110
with gate electrode in salicide (self-aligned silicide) process.
FIG. 2
is a case of showing a result of bridge between gate electrode and source/drain region
110
in a salicide process. A salicide layer
142
, such as titanium salicide or cobalt salicide, is formed by depositing a metal layer, titanium or cobalt respectively, on the substrate
100
and performing a RTA (rapid thermal anneal) process. Metal layer will react will poly gate
124
and silicon on source/drain
110
to form silicide layer
142
.
However, if metal layer is deposited excessively, there may be undue metal between gate and source/drain region
110
to conduct gate and source/drain region
110
. This is usually occurred when spacer
130
is oblique, or the device dimension is scaled down. Therefore, this issue must be solved.
SUMMARY OF THE INVENTION
In accordance with the present invention, it is a main object of this invention to form steep spacer in a MOS device that substantially prevents S/D and gate bridging.
It is another object of this invention that steep spacer is very desirable in the salicide process as the device dimension scaled down.
In one embodiment, a method for forming a steep spacer in a metal-oxide-semiconductor device is disclosed. The method includes a first step of depositing a first conformal dielectric layer on a substrate having a gate electrode structure formed thereon. A gate electrode structure, including a gate dielectric layer and a poly gate layer. The first conformal dielectric layer may be TEOS or silicon nitride. Then, a second conformal dummy layer is deposited on the first conformal dielectric layer. During etching, the second conformal dummy layer must have different selectivity to the first conformal dielectric layer. Next, the second conformal dummy layer is anisotropically etched to form a first spacer on sidewall of the first conformal dielectric layer, and the first conformal dielectric layer is then anisotropically etched by using the first spacer as a mask to form a second spacer on sidewall of the gate electrode structure. The first spacer is removed and the second spacer is therefore steep.


REFERENCES:
patent: 6090692 (2000-07-01), Song
patent: 6150223 (2000-11-01), Chern et al.
patent: 6383881 (2002-05-01), Akram et al.

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