Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-10-02
2002-09-03
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S613000
Reexamination Certificate
active
06444561
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for forming solder bumps for a flip-chip bonding process and structures formed and more particularly, relates to a method for forming solder bumps that have substantially the same height for flip-chip bonding wherein a gap for flowing an underfill material in-between a chip and a substrate is increased to reduce fill time and structures formed by the method.
BACKGROUND OF THE INVENTION
In the fabrication of modern semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques in such high density devices. Conventionally, a flip-chip attachment method has been used in packaging of semiconductor chips. In the flip-chip attachment method, instead of attaching a semiconductor die to a lead frame in a package, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out in an evaporation method by using a composite material of tin and lead through a mask for producing a desired pattern of solder bumps. The technique of electrodeposition has been more recently developed to produce solder bumps in flip-chip packaging process.
Other techniques that are capable of solder-bumping a variety of substrates to form solder balls have also been proposed. The techniques generally work well in bumping semiconductor substrates that contain solder structures over a minimal size. For instance, one of such widely used techniques is a solder paste screening method which has been used to cover the entire area of an eight inch wafer. However, with recent trend in the miniaturization of device dimensions and the necessary reduction in bump-to-bump spacing (or pitch), the use of the solder paste screening technique has become more difficult.
Other techniques for forming solder bumps such as the controlled collapse chip connection (C4) technique and the thin film electrodeposition technique have also been used in recent years in the semiconductor fabrication industry. The C4 technique is generally limited by the resolution achievable by a molybdenum mask which is necessary for the process. Fine-pitched solder bumps are therefore difficult to be fabricated by the C4 technique. Similarly, the thin film electrodeposition technique which also requires a ball limiting metallurgy layer to be deposited and defined by an etching process which has the same limitations as the C4 technique.
For instance, in a conventional thin film electrodeposition process for depositing solder bumps, bond pads are first formed on a top surface of a substrate for making electrical connections to the outside circuits. The bond pads are normally formed of a conductive metal such as aluminum. The bond pads may be passivated in a passivation layer with windows opened by a photolithography process to allow electrical connections to be made to the bond pads. The passivation layer may be formed of any one of various insulating materials such as oxide, nitride or organic materials. The passivation layer is applied on top of the semiconductor device to provide both planarization and physical protection of the circuits formed on the device. Onto a top surface of the passivation layer and an exposed top surface of the bond pads, is then deposited an under bump metallurgy (UBM) layer. The under bump metallurgy layer normally consists of an adhesion/diffusion barrier layer and a wetting layer. The adhesion/diffusion barrier layer may be formed of Ti, TiN or other metal such as Cr. The wetting layer is normally formed of a Cu layer or a Ni layer. The UBM layer improves bonding between a solder ball to be formed and the top surface of the bond pads.
In the next step of the process, a photoresist layer is deposited on top of the UBM layer and patterned to define window openings for the solder balls to be subsequently formed. In the following electrodeposition process, solder balls are electro-deposited into window openings forming a structure protruding from the top surface of the photoresist layer. The use of the photoresist layer must be carefully controlled such that its thickness is in the range between about 30 &mgr;m and about 40 &mgr;m, or preferably a thickness of about 35 &mgr;m. The reason for the tight control on the thickness of the photoresist layer is that, for achieving a fine-pitched solder bump formation, a photoresist layer of a reasonably small thickness must be used so that high imaging resolution can be achieved. It is known that, during a photolithography process, the thicker the photoresist layer, the poorer is the imaging process achieved. To maintain high accuracy in the imaging process on the photoresist layer, reasonably thin photoresist layer must be used resulting in a mushroom configuration of the solder bump deposited therein. The mushroom shape of the solder bump contributes to the inability of a conventional process in producing fine-pitched solder bumps.
The photoresist layer is then removed in a wet stripping process. The mushroom-shaped solder bump remains while the UBM layer is also intact. In the next step of the process, the UBM layer is etched away by using the solder bumps as a mask in a wet etching process. The solder bumps are then heated in a reflow process to form solder balls. The reflow process is conducted at a temperature that is at least the reflow temperature of the solder material.
In recent years, chip scale packages (CSP) have been developed as a new low cost packaging technique for high volume production of IC chips. One of such chip scale packaging techniques has been developed by the Tessera Company for making a so-called micro-BGA package. The micro-BGA package can be utilized in an environment where several of the packages are arranged in close proximity on a circuit board or a substrate much like the arrangement of individual tiles. Major benefits achieved by a micro-BGA package are the combined advantages of a flip chip assembly and a surface mount package. The chip scale packages can be formed in a physical size comparable to that of an IC chip even though, unlike a conventional IC chip such as a flip chip, the chip scale package does not require a special bonding process for forming solder balls. Furthermore, a chip scale package may provide a larger number of input/output terminals than that possible from a conventional quad flat package.
In a typical micro-BGA package, a flexible interposer or underfill layer (which may contain circuit) is used to interconnect bond pads on an IC chip to an array of solder bump connections located on a flexible circuit. The flexible circuit, normally of a thickness of approximately 25 &mgr;m, is formed of a polymeric material such as polyimide which is laminated to a silicon elastomer layer of approximately 150 &mgr;m thick. The silicon elastomeric layer provides flexibility and compliance in all three directions for relief of stresses and thermal expansion mismatches. To further reduce the fabrication cost of IC devices, it is desirable that if a whole wafer can be passivated to seal the IC dies on the wafer, and then be severed into individual IC dies from the wafer such that not only the benefits of a chip scale package can be realized, the packaging cost for the IC dies may further be reduced.
The conventional method for depositing solder bumps described above utilizing solder masks presents a number of processing difficulties. For instance, one of the difficulties is the possible misalignment of a solder mask used during a solder bump deposition process. This is shown in
FIGS. 1 and 3
. For instance,
FIGS. 1A and 1B
illustrate a conventional solder masking process that does not have a solder mask misalignment problem. When a solder mask
10
is positioned on a semiconductor substrate
20
which has a metal trace
22
and a bond pad
24
formed on a top surface, an opening
12
in the solder mask
10
should be aligned with the bond pad
24
. Under an ideal processing condition shown in
FIGS. 1A and 1B
, th
Chang Chung-Tao
Chen Kuo-Chuan
Wang Chia-Chung
Industrial Technology Research Institute
Niebling John F.
Roman Angel
Tung & Associates
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