Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-11-06
2007-11-06
Estrada, Michelle (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S675000, C438S201000, C257SE21649, C257SE27084, C257S071000
Reexamination Certificate
active
10873388
ABSTRACT:
A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug. Phase-change memory devices formed by such techniques are also discussed.
REFERENCES:
patent: 3877049 (1975-04-01), Buckley
patent: 5244534 (1993-09-01), Yu et al.
patent: 5440167 (1995-08-01), Iranmanesh
patent: 5776833 (1998-07-01), Chen et al.
patent: 5789758 (1998-08-01), Reinberg
patent: 6147395 (2000-11-01), Gilgen
patent: 6274485 (2001-08-01), Chen et al.
patent: 6806528 (2004-10-01), Lee et al.
patent: 6833331 (2004-12-01), Saito et al.
patent: 6884735 (2005-04-01), Okoroanyanwu et al.
patent: 6972262 (2005-12-01), Lee et al.
patent: 7037762 (2006-05-01), Joo et al.
patent: 2001/0004066 (2001-06-01), Toshima et al.
patent: 63272037 (1988-11-01), None
patent: 2003-174144 (2003-06-01), None
Park et al, Study of Over-Polishing at the Edge of a Pattern in Selective CMP, Sixth International Symposium on Chemical Mechanical Polishing, 204thMeeting of the Electrochemical Society, Inc., Oct. 12-16, 2003, 8 pages.
Hwang et al, “Completely CMOS-Compatible Phase-Change Nonvolatile RAM Using NMOS Cell Transistors,” Non-Volatile Semiconductor Memory Workshop, Feb. 2003, pp. 91-92.
Hwang et al, “Phase Change Chalcogenide Nonvolatile RAM Completely Based on CMOS Technology,” VLSI Symposium, Jun. 2003, 3 pages.
Park et al., “Study of Over-polishing at the Edge of a Pattern in Selective CMP,” Abs. 930, 204thMeeting of the Electrochemical Society, Inc., Oct 12-16, 2003, 1 page.
Cho Sung-Lae
Choi Suk-Hun
Park Joon-Sang
Son Yoon-Ho
Estrada Michelle
Myers Bigel & Sibley Sajovec, PA
Samsung Electronics Co,. Ltd.
Tobergte Nicholas J.
LandOfFree
Method for forming small features in microelectronic devices... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming small features in microelectronic devices..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming small features in microelectronic devices... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3810261