Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1998-09-21
2001-10-02
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S533000, C438S586000, C438S655000, C438S657000, C438S659000, C438S661000
Reexamination Certificate
active
06297135
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is directed to a method for forming silicide regions for low-resistance electrical connections to integrated devices formed on silicon substrates. The reduced contact resistances provide the devices with the capability to operate at relatively high speeds.
2. Description of the Related Art
Many techniques have been developed for forming silicide regions for integrated device contacts, particularly for metal-oxide-semiconductor (MOS) devices formed on silicon substrates. Most of these techniques involve the formation of a metal layer over gate, drain or source regions upon which the silicide is desired to be formed. These techniques then use thermal treatment for extended periods of time to react the metal with the silicon composing the gate, drain and/or source regions, to form the low-resistivity silicide regions. The substrate is further processed by removing the unreacted metal layer.
Techniques for forming silicides are subject to several stringent process constraints that must be met in order for such techniques to be effective. These constraints include: (1) the metal used to form the silicide and the temperature at which the silicide is formed must be carefully selected so that the metal diffuses into the silicon, to avoid the formation of leakage paths between the source, drain and gate of an integrated device; (2) for self-aligned silicidation techniques, the metal layer must not react with the insulating material composing the side walls of the gate; (3) the dopants must not segregate appreciably into the silicide regions so that low contact resistance can be achieved; (4) the technique should have a process window that allows the silicide region to be formed on both c-silicon and poly-silicon; (5) the silicide formation should be insensitive to dopants present in the silicon; and (6) the metal atoms should not diffuse beyond the silicide regions to prevent increase in junction leakage. The simultaneous achievement of all of the above-stated criteria is at best difficult for most conventional silicidation techniques, especially those that use relatively extensive thermal treatments. Most often, a failure to perform the conventional technique within its relatively narrow process margins manifests itself in the occurrence of defects due to thermal drift of the metal atoms beyond desired boundaries during the relatively prolonged thermal treatment periods required by such techniques. If the silicide region extends beyond its design dimensions, it can cause leakage paths between the gate, source/drain and the substrate. There is therefore a great need for a technique that enhances silicidation process margins beyond those conventionally available.
In addition to conventional techniques that use prolonged thermal treatments, some conventional silicidation techniques use ion implantation to achieve formation of the silicide regions. These ion-implantation silicidation techniques use either ion beam mixing of different ion types to produce a silicide of a desired composition, or implantation of a desired species of metal ions in a proportion needed to achieve proper stoichiometry. In either of these two types of techniques, the ion-implantation is so extensive as to be extremely time-consuming, especially if a stoichiometric proportion of ions needed to make the silicide must be implanted into the silicon substrate. In addition, extensive ion implantation will eventually lead to ‘knock-on’, a phenomenon in which moving ions strike ions previously implanted, driving them further than desired into the silicon substrate. The occurrence of knock-on leads to increased junction leakage. Thus, there is a significant need for a technique that can overcome the above-noted disadvantages of conventional silicidation techniques.
A constraint of the silicidation techniques discussed above is that the silicide thickness over the gate and the polysilicon runners is the same as that over the source/drain regions. As source/drain junctions are scaled to shallower depths, the silicide thickness over the source/drain also needs to be lowered to prevent leakage. However, silicide thickness scaling is not necessary over the gate region and it is in fact advantageous to have thicker silicide over the gate than the source/drain. Such a silicide can be formed either by depositing a thicker metal layer over the gate than the source/drain, or by subjecting the gate to a higher thermal budget. Neither of these two options are feasible using conventional silicide formation techniques.
SUMMARY
This invention overcomes the above-noted disadvantages. A preferred embodiment of the invented method includes a step of producing amorphous regions on the gate, source, drain and runner(s) of an integrated device formed on a silicon substrate. The method also includes a step of forming a metal layer in contact with the amorphous regions, and a step of selectively irradiating the metal layer with light to diffuse metal into the gate, and amorphous source and drain regions to form respective alloy regions of silicide composition. The method further includes a step of blanket irradiating the metal layer with light to diffuse metal into the runners to form an alloy region therein. Through two-step irradiation, high-quality suicides can be produced on the gate, source, drain and runner regions despite the typically large differences in laser fluence required to form silicide over the gate, source and drain relative to the runner(s).
In general, silicidation proceeds more rapidly in the gate region as compared to the source and drain regions because the gate region is more thermally insulated as compared to the source and drain regions which are integral with the substrate that acts as a heat sink. With the invented method, however, the fluence required for silicidation in the gate is raised if the gate region extends beyond, and/or is coupled to a runner situated outside of, the selectively irradiated area. The portion of the gate region and/or coupled runner that is not irradiated is relatively cool and thus acts as a heat sink to draw heat away from the gate region. Accordingly, the fluence required for silicidation of the gate can be raised to more closely correspond to the fluence required for silicidation in the source and drain. By forcing the respective fluences for silicidation required in the gate, source and drain closer to one another in the invented method, relatively high-quality silicides can be formed together in the gate, source, and drain of the integrated device.
Preferably, the light fluence used in the selective radiation step is determined so that sufficient energy is absorbed by the metal layer to melt the amorphous regions of the source/drain and part of the gate region until the metal layer overlying the gate region is consumed, at which point the increased reflectivity of the gate alloy (especially in its liquid state) is sufficient to prevent further melting of the gate alloy region. By preventing further significant melting beyond the alloy region, the silicide in the gate region is relatively stoichiometric and has a low sheet resistance. Also, if desired, the selective irradiation step can be continued to allow further growth of the silicide regions in the source and drain without adversely impacting the gate region due to its increased reflectivity upon exposure of the alloy region resulting from consumption of the overlying metal.
Similarly, the blanket irradiation step can be performed at least until the metal layer overlying the runner is consumed. The fluence of the blanket irradiation step is preferably selected so that, upon consumption of the metal layer overlying the runner, the exposed silicide alloy region, especially in its liquid state, reflects sufficiently more light as compared to the metal layer to prevent further melting of the runner region. Because the runner is generally located on a field isolation layer that has relatively poor thermal conductivity, the silicide growth rate in the runner region is
Kramer Karl-Josef
Talwar Somit
Verma Gaurav
Weiner Kurt
Berry Renee R.
Jones Allston L.
Nelms David
Ultratech Stepper, Inc.
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