Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-07-05
2005-07-05
Chaudhari, Chandra (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S426000
Reexamination Certificate
active
06913978
ABSTRACT:
A method of fabricating a shallow trench isolation structure is disclosed. On a substrate, a pad oxide layer and a mask layer are successively formed. The pad oxide layer, the mask layer and a portion of the substrate are patterned to form a trench. After performing a rapid wet thermal process, a liner layer is formed on the exposed surface of the substrate, including the exposed silicon surface of the substrate in the trench and sidewalls and the surface of the mask layer. An oxide layer is deposited over the trench and the substrate and fills the trench. A planarization process is performed until the mask layer is exposed. The mask layer and the pad oxide layer are removed to complete the shallow trench isolation structure.
REFERENCES:
patent: 6017800 (2000-01-01), Sayama et al.
patent: 6074931 (2000-06-01), Chang et al.
patent: 6258676 (2001-07-01), Lee et al.
patent: 6468853 (2002-10-01), Balasubramanian et al.
patent: 6790746 (2004-09-01), Yang
Chen Neng-Kuo
Chu Hsiu-Chuan
Huang Chih-An
Lu Hsiao-Ling
Tsai Teng-Chun
Chaudhari Chandra
J.C. Patents
United Microelectronics Corp.
LandOfFree
Method for forming shallow trench isolation structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming shallow trench isolation structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming shallow trench isolation structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3377646