Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Patent
1998-01-29
2000-07-11
Mulpuri, Savitri
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
438795, 438514, H01L 21477
Patent
active
060872470
ABSTRACT:
A method is provided for forming a shallow junction in a semiconductor wafer that has been implanted with a dopant material. The dopant material is activated by thermal processing of the semiconductor wafer in a thermal processing chamber at a selected temperature for a selected time. The oxygen concentration in the thermal processing chamber during activation of the dopant material is controlled at or near a selected level less than a background level that is typically present when the thermal processing chamber is filled with a process gas. The oxygen concentration may be controlled at or near a selected level in a range less than 1000 parts per million and is preferably controlled at or near a selected level in a range of about 30-300 parts per million. The method is particularly useful for implanted boron or BF.sub.2 ions, but may be used for any dopant material.
REFERENCES:
patent: 4625450 (1986-12-01), Tani et al.
patent: 5279973 (1994-01-01), Suizu
M. I. Current, et al, "20 da eV (200eV) to 10 keV Boron Implantation and Rapid Thermal Annealing of Si(100); A SiMS and TEM Study", 4th Intl. Workshop-Meas., Char.&Modeling of Ultra-Shallow Doping Profiles, Apr. 1997, pp. 41.4 to 41.12.
E. J. H. Collart et al, "Char. of Low Energy (100 eV-10 keV) Boron Ion Implantation", 4th Intl. Workshop-Meas. Char. & Modeling of Ultra-Shallow Doping Profiles, Apr. 1997, pp. 6.1 to 6.9.
A. Agarwal et al, "Boron Enhanced Diffusion of Boron: The Limiting Factor for Ultra-Shallow Junctions", IEDM 97, 1997, pp. 467-470.
Daniel F. Downey et al, "Rapid Thermal Process Req. for the Annealing of Ultra-Shallow Junctions", Varian Assoc., Inc., Report No. 298, Mat. Research Soc. Symp., Apr. 1997.
S. S. Todorov et al, "Optimization of RTP Annealing of Low-Energy BF.sub.2 and Boron Implants", Proc. of RTP '97 5th Int'l. Conf. on Advanced Thermal Processing of Semiconductors, Sep. 1997.
S. D. Marcus et al, "Rapid Thermal Annealing of Low Energy As Implants", Proc. of RTP '97, 5th Int'l. Conf. on Advanced Thermal Processing of Semiconductors, Sep. 1997.
C. W. Magee et al, "Analytical Techniques to Detect Boron Dopant Loss in Ultra-Shallow Junctions as a Function of Post Doping Processing", Proc. of 4th Int'l. Workshop on Ultra-Shallow Junctions, Apr. 1997, p. 8.1.
Mulpuri Savitri
Varian Semiconductor Equipment Associates Inc.
LandOfFree
Method for forming shallow junctions in semiconductor wafers usi does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming shallow junctions in semiconductor wafers usi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming shallow junctions in semiconductor wafers usi will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-541862