Method for forming semiconductor dielectric layer

Details Method for forming semiconductor dielectric layer Method for forming semiconductor dielectric layer

1998-05-08

2001-07-03

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

C438S786000

Reexamination Certificate

active

06255229

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 87102845, filed Feb. 27, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for forming an integrated circuit structure. More particularly, the present invention relates to a method for forming a semiconductor dielectric layer using silicon-oxy-nitride (SiO
x
N
y
) rather than the conventional silicon nitride (Si
3
N
4
), thereby eliminating some of the defects of a conventional manufacturing process.
2. Description of Related Art
In the fabrication of very large scale integration (VLSI) circuits, hundreds of thousand of metal oxide semiconductor (MOS) transistors can be packed within an area just 1 to 2 cm
2
on the wafer surface. As the level of integration is further increased, the density of metallic lines that are used for interconnecting various transistors or other electronic devices in the integrated circuit will also get higher. These vast numbers of metallic interconnection lines are going to cross over a variable number of inter-layer dielectric (ILD) layers in order to provide the necessary connectivity.
In the conventional VLSI manufacturing technique, the insulating layer within which contact openings or interconnects are formed is usually a dielectric material with a dielectric constant approaching 1. Preferably, the inter-layer dielectric layer is formed by a chemical vapor deposition (CVD) method, and then the layer is planarized. Finally, the ILD layer is patterned to form the necessary contact openings for subsequent deposition of polysilicon or metal. Typical material suitable for forming contact openings in the inter-layer dielectric layer includes silicate glass preferably deposited to a thickness of between 5000 Å to 10000 Å. Examples of the silicate glass material include boro-phospho-silicate glass (BPSG) and phospho-silicate glass (PSG). When these inter-layer dielectric materials are heated to a temperature higher than their respective glass transition temperatures, for example, between 700° C. to 900° C., these materials will density and reflow.
Normally, to lower the reflow temperature of silicate glass, a small amount of dopants is added. For example, phosphorus or phosphorus-containing organic compound such as trimethylphosphate (TMP) is used as a dopant to form phospho-silicate glass and a boron-containing compound such as trimethylborate (TMB) and phosphorus-containing organic compound are used as dopants to form boro-phospho-silicate glass (BPSG). Reflow of the inter-layer dielectric layer is necessary. Reflow enables the inter-layer dielectric material to flow smoothly over surfaces, thus permitting various devices to be covered and allowing gaps formed between interconnecting lines to be filled. Furthermore, reflow serves to provide a planarized surface for subsequent processing operations.
Phospho-silicate glass is mainly used as a passivation layer in the fabrication of VLSI circuits. This is because phospho-silicate glass has the ability to easily absorb water. However, phospho-silicate glass has a reflow temperature (greater than 1000° C.) very much higher than boro-phospho-silicate glass (less than 1000° C.). Therefore, most inter-layer dielectric layers are still formed using boro-phospho-silicate glass.
Normally, in a conventional fabricating method, a silicon nitride layer is deposited between a first inter-poly dielectric (IPD1) and a second inter-poly dielectric (IPD2) before a contact opening is formed. Preferably, the first inter-poly dielectric layer is a boro-phospho-silicate glass layer, which acts as the main body of the inter-layer dielectric layer and the second inter-poly dielectric layer is a phospho-silicate glass, a which serves as a passivation layer. The silicon nitride layer can act as an etching mask when a silicon dioxide layer is etched. Furthermore, the silicon nitride layer can serve as a protective layer preventing charging, which can lead to a change in the threshold voltage, when the second inter-poly dielectric (PSG layer) is deposited.
Although the formation of a silicon nitride layer in a conventional fabricating process is able to prevent the charging problem, the deposited silicon nitride layer has a rather high tensile stress of up to 10
10
dyne/cm
2
. This is especially serious for a silicon nitride layer formed by a low-pressure chemical vapor deposition (LPCVD) method. Consequently, whenever the tensile stress of the deposited silicon nitride thin film is beyond a certain tensile threshold boundary, cracks may appear which can affect subsequent semiconductor fabrication.
In addition, because a silicon nitride layer has a lower etching rate than an interpoly poly dielectric layer, etching will almost stop when the silicon nitride layer is reached during the etching operation to form a contact opening. Hence, the whole etching operation will be affected.
In light of the foregoing, there is a need to provide a better semiconductor dielectric layer.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide a method for forming a semiconductor dielectric layer using silicon oxy-nitride instead of silicon nitride as the basic material. The silicon oxy-nitride layer, besides being capable of avoiding the formation of cracks, is also able to prevent the etching stop problem due to a difference in etching rate relative to surrounding layers.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for forming a semiconductor dielectric layer. The method comprises the steps of first providing a substrate having a plurality of semiconductor devices already formed thereon, and then forming a first dielectric layer over the substrate. Next, a silicon oxy-nitride layer is formed over the first dielectric layer, and then a second dielectric layer is formed over the silicon oxy-nitride layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5930627 (1999-07-01), Zhou et al.
patent: 5972800 (1999-10-01), Hasegawa

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