Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-02-19
1999-11-30
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438275, 438302, H01L 218238
Patent
active
059941766
ABSTRACT:
The method of forming a MOS transistor in a semiconductor substrate with the self-aligned silicide contact for ESD protection includes the following steps. At first, an isolation region is formed to separate an ESD protective region and a functional region. A gate insulator layer and a polysilicon layer are formed. The polysilicon layer is then patterned to form a gate structure. The substrate is doped to form a lightly doped region and the ESD protective region is then doped to have a junction region. A covering layer is then formed over the ESD protective region and a first dielectric layer is formed. A portion of the first dielectric layer is removed to form a spacer structure. A silicidation process is performed to form a metal silicide layer and the metal silicide layer is then doped. A second dielectric layer is formed and a thermal process is then performed to form a junction region in the functional region.
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Murphy John
Niebling John F.
Texas Instruments - Acer Incorporated
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